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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit pd30181a, 30181ay v r 4181a tm 64-/32-bit microprocessor data sheet ? 2002 ? 1997 the mark shows major revised points. document no. u16277ej1v0ds00 (1st edition) date published october 2002 n cp(k) printed in japan description the pd30181a and 30181ay (v r 4181a), which are high-performance 64-/32-bit microprocessors employing the risc (reduced instruction set computer) architecture developed by mips tm , are products in the v r series tm of microprocessors manufactured by nec. the v r 4181a includes as its cpu the v r 4120? core, an ultra-low-power-consumption core featuring cache memory, a high-speed product-sum operation unit, and a memory management unit. other on-chip components include an lcd controller, compactflash controller, usb host/function controller, dma controller, sdram controller, pwm controller, ac97/i 2 s audio interface, full-duplex asynchronous serial interface, irda interface, i 2 c serial interface, keyboard interface, touch panel interface, real-time clock, a/d converter, d/a converter, and other controllers and interfaces required for battery-driven mobile information devices, fixed compact information devices, car navigation systems, and compact embedded devices. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. ? ? ? ? v r 4181a hardware user?s manual (u16049e) ? ? ? ? v r 4100 series tm architecture user?s manual (u15509e) features { v r 4120 core (64-bit risc core) on chip as cpu { pipeline clock: 131 mhz { conforms to mips iii (except for fpu, ll and sc instructions) and mips16 instruction sets { supports macc and dmacc high-speed product-sum operation instructions { on-chip cache memory capacity includes 8 kb instruction cache and 8 kb data cache { employs a writeback cache { physical addresses: 32 bits virtual addresses: 40 bits { on-chip 32 double-entry tlb { effective power management using four modes: fullspeed, standby, suspend, and hibernate { employs a high-performance internal system bus (t- bus) { dram controller supporting 64 mb, 128 mb, and 256 mb sdrams { external system bus interface supporting rom, page rom, flash memory, sram, isa devices, ide (ata) devices, and syncflash? memory { uma type lcd controller (supports stn and tft panels) { exca register-compatible compactflash interface (2 slots) { usb host controller (rev1.1, ohci rev1.0) controller { usb function (rev1.1) controller { ac97 and i 2 s audio interfaces (1 channel each) { clocked serial interface (1 channel) { ns16550-compatible serial interface (3 channels) { irda (sir) interface (1 channel) { i 2 c bus interfaces (2 channels, pd30181ay only) { pwm controller (3 channels) { dma controller supporting chain mode (4 channels) { keyboard scan interface (supports 8 12 key matrix) { x-y coordinate auto scan touch panel interface { on-chip a/d converter and d/a converter { on-chip watchdog timer unit { rtc unit (total of 3 timer and counter channels) { on-chip pll and clock generators { power supplies: 2.5 v for core, 3.3 v for i/o block { package: 240-pin plastic fbga
data sheet u16277ej1v0ds 2 pd30181a, 30181ay applications { car navigation systems { digital consumer devices (digital information home equipment) { battery-driven mobile information devices { controllers for embedded devices ordering information part number package i 2 c bus interface internal maximum operating frequency pd30181af1-131-ga3 240-pin plastic fbga (16 16) none 131 mhz pd30181af1-131-ga3-a note 240-pin plastic fbga (16 16) none 131 mhz pd30181ayf1-131-ga3 240-pin plastic fbga (16 16) on chip 131 mhz pd30181ayf1-131-ga3-a note 240-pin plastic fbga (16 16) on chip 131 mhz note lead-free product pin configuration ? 240-pin plastic fbga (16 16) bottom view top view 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 index mark vutrpnmlk jhgfedcba abcdefghj klmnprtuv
data sheet u16277ej1v0ds 3 pd30181a, 30181ay (1/3) no. power supply name no. power supply name a1 3.3 v d6 c5 3.3 v d26 a2 3.3 v d5 c6 3.3 v d24 a3 3.3 v d3 c7 3.3 v d23 a4 3.3 v d1 c8 3.3 v d22 a5 3.3 v d8 c9 3.3 v d20 a6 3.3 v d10 c10 3.3 v d18 a7 3.3 v d12 c11 3.3 v uhdp a8 3.3 v d14 c12 3.3 v uoc a9 3.3 v d16 c13 3.3 v nmi# a10 3.3 v d17 c14 3.3 v dqm2/lbe2# a11 3.3 v udp c15 3.3 v pcs0# a12 3.3 v clk48 c16 3.3 v sysen# a13 3.3 v sdcs2# c17 3.3 v iordy a14 3.3 v sdcs3# c18 3.3 v ube# a15 3.3 v memwr# d1 3.3 v cas# a16 3.3 v pcs4# d2 3.3 v ras# a17 3.3 v pcs1# d3 3.3 v d29 a18 3.3 v iord# d4 2.5 v vdd2 b1 3.3 v d7 d5 3.3 v d25 b2 3.3 v dqm1/lbe1# d6 2.5 v gnd2 b3 3.3 v d4 d7 2.5 v vdd2 b4 3.3 v d2 d8 3.3 v d21 b5 3.3 v d0 d9 3.3 v d19 b6 3.3 v d9 d10 3.3 v gndu b7 3.3 v d11 d11 3.3 v vddu b8 3.3 v d13 d12 3.3 v gnd3 b9 3.3 v d15 d13 3.3 v vdd3 b10 3.3 v udn d14 2.5 v gnd2 b11 3.3 v uhdn d15 3.3 v memrd# b12 3.3 v upon d16 3.3 v pwm1/kscan6/gpio9 b13 3.3 v dqm3/lbe3# d17 3.3 v iocs16# b14 3.3 v pcs3# d18 3.3 v pwm0/kscan7/gpio8 b15 3.3 v romcs# e1 3.3 v sdclk b16 3.3 v pcs2# e2 3.3 v sdcs1# b17 3.3 v sysdir e3 3.3 v d30 b18 3.3 v iowr# e4 3.3 v vdd3 c1 3.3 v dqm0/lbe0# e8 3.3 v vdd3 c2 3.3 v we# e9 3.3 v gnd3 c3 3.3 v d28 e10 2.5 v gnd2 c4 3.3 v d27 e11 2.5 v vdd2 remark # indicates active low.
data sheet u16277ej1v0ds 4 pd30181a, 30181ay (2/3) no. power supply name no. power supply name e15 3.3 v vdd3 k2 3.3 v a12 e16 3.3 v kport0/gpio4 k3 3.3 v a19/gpio58 e17 3.3 v pwm2/kscan5/gpio10 k4 3.3 v a20/gpio59 e18 3.3 v kport1/gpio5 k5 3.3 v vdd3 f1 3.3 v sdcs0# k14 3.3 v vdd3 f2 3.3 v cke0 k15 3.3 v so/kscan9/gpio21 f3 3.3 v d31 k16 3.3 v sck/kscan11/gpio23 f4 3.3 v gnd3 k17 3.3 v frm/kscan8/gpio20 f15 2.5 v gndp k18 3.3 v cf1_vccen#/kscan4/gpio37 f16 3.3 v cf1_dir/kport4/gpio39 l1 3.3 v a11 f17 3.3 v kport2/gpio6 l2 3.3 v a9 f18 3.3 v clkx1 l3 3.3 v a17/gpio56 g1 3.3 v a13 l4 3.3 v a18/gpio57 g2 3.3 v a14 l5 2.5 v vdd2 g3 3.3 v tc0#/gpio52 l14 2.5 v gnd2 g4 3.3 v tc1#/gpio53 l15 3.3 v jtms g15 2.5 v vddp l16 3.3 v jtdo g16 3.3 v kport3/gpio7 l17 3.3 v si/kscan10/gpio22 g17 3.3 v cf1_en#/kport5/gpio38 l18 3.3 v jtck g18 3.3 v clkx2 m1 3.3 v a8 h1 3.3 v sa10 m2 3.3 v a7 h2 3.3 v a0 m3 3.3 v a15/gpio54 h3 3.3 v a23/rp# m4 3.3 v a16/gpio55 h4 3.3 v a24/cke1 m15 3.3 v jtrst# h5 2.5 v gnd2 m16 3.3 v cf0_iois16#/gpio34 h14 3.3 v vddo m17 3.3 v jtdi/rmode# h15 3.3 v gndo m18 3.3 v bktgio# h16 3.3 v kscan0/gpio0 n1 3.3 v a6 h17 3.3 v kscan3/gpio3 n2 3.3 v a5 h18 3.3 v rtcx2 n3 3.3 v a10 j1 3.3 v a1 n4 2.5 v gnd2 j2 3.3 v a2 n15 2.5 v vdd2 j3 3.3 v a21/gpio60 n16 3.3 v cf0_cd2#/gpio36 j4 3.3 v a22/gpio61 n17 3.3 v cf0_cd1#/gpio35 j5 3.3 v gnd3 n18 3.3 v cf_wait#/gpio33 j14 2.5 v vdd2 p1 3.3 v a4 j15 3.3 v gnd3 p2 3.3 v dak1# j16 3.3 v kscan1/gpio1 p3 3.3 v drq1# j17 3.3 v kscan2/gpio2 p4 3.3 v gndad j18 3.3 v rtcx1 p8 2.5 v vdd2 k1 3.3 v a3 p9 2.5 v gnd2 remark # indicates active low.
data sheet u16277ej1v0ds 5 pd30181a, 30181ay (3/3) no. power supply name no. power supply name p10 2.5 v gnd2 t16 3.3 v fpd2 p11 3.3 v gnd3 t17 3.3 v i.c. (gnd3) note 2 p15 3.3 v cf0_ce2#/gpio32 t18 3.3 v cf0_en#/gpio26 p16 3.3 v cf0_dir/gpio27 u1 3.3 v mpower p17 3.3 v cf0_ready/gpio29 u2 3.3 v ain0 p18 3.3 v cf0_ce1#/gpio31 u3 3.3 v tpx0 r1 3.3 v drq0# u4 3.3 v tpy0 r2 3.3 v power u5 3.3 v txd0/clksel2 note 1 r3 3.3 v rstsw# u6 3.3 v rts0#/gpio19/clksel1 note 1 r4 3.3 v gndtp u7 3.3 v rxd2/irdin r5 3.3 v vddtp u8 3.3 v cts2#/bitclk/sclk r6 3.3 v vddad u9 3.3 v i.c. (gnd3) note 2 r7 3.3 v vdd3 u10 3.3 v scl0/kport7/gpio12 r8 3.3 v gnd3 u11 3.3 v vsync/flm/bmode1 note 1 r9 3.3 v dcd2#/sdatain/sdi u12 3.3 v fpd15/cf1_ready/gpio51 r10 3.3 v sda0/kport6/gpio11 u13 3.3 v fpd12/cf1_ce1#/gpio48 r11 3.3 v vpbias/gpo63 u14 3.3 v fpd10/cf1_cd1#/gpio46 r12 3.3 v vplcd/gpo62 u15 3.3 v fpd6/gpio42 r13 3.3 v vdd3 u16 3.3 v fpd4/gpio40 r14 2.5 v vdd2 u17 3.3 v cf1_reset/dbus32 note 1 r15 3.3 v gnd3 u18 3.3 v cf0_vccen#/gpio24 r16 3.3 v cf_reg#/gpio25 v1 3.3 v tpy1 r17 3.3 v cf0_reset/gpio28 v2 3.3 v ain1 r18 3.3 v cf0_stschg#/gpio30 v3 3.3 v ain3 t1 3.3 v rtcrst# v4 3.3 v aout t2 3.3 v poweron v5 3.3 v rxd0 t3 3.3 v dak0# v6 3.3 v cts0#/gpio18 t4 3.3 v tpx1 v7 3.3 v dtr0#/rts1#/gpio17/clksel0 note 1 t5 3.3 v ain2 v8 3.3 v txd2/irdout/mips16en note 1 t6 3.3 v dcd0#/gpio16 v9 3.3 v dsr2#/sreset# t7 3.3 v dsr0#/cts1#/gpio15 v10 3.3 v rxd1/scl1/gpio14 t8 3.3 v rts2#/sync/ws/divmode1 note 1 v11 3.3 v dclk/shclk t9 3.3 v dtr2#/sdataout/sdo/divmode0 note 1 v12 3.3 v hsync/loclk/nwireen note 1 t10 3.3 v txd1/sda1/gpio13 v13 3.3 v fpd11/cf1_cd2#/gpio47 t11 3.3 v enab/m/bmode0 note 1 v14 3.3 v fpd9/gpio45 t12 3.3 v fpd14/cf1_stschg#/gpio50 v15 3.3 v fpd7/gpio43 t13 3.3 v fpd13/cf1_ce2#/gpio49 v16 3.3 v fpd5/gpio41 t14 3.3 v fpd8/gpio44 v17 3.3 v fpd3 t15 3.3v fpd0 v18 3.3 v fpd1 notes 1. these pins are used for mode settings. a mode setting is made according to the status of these pins at the rising edge of the rtcrst# signal. use pull-up/pull-down resistors to set the pin statuses. 2. be sure to connect these pins to gnd3. remark # indicates active low.
data sheet u16277ej1v0ds 6 pd30181a, 30181ay pin indentification (1/2) a(24:0): address bus ain(3:0): analog data input aout: analog data output bitclk: ac97 bit clock bktgio#: n-wire break trigger i/o bmode(1:0): boot mode cas#: sdram column address strobe cf_reg#: compactflash register memory access cf_wait#: compactflash wait input cf0_cd(2:1)#: compactflash card detect cf0_ce(2:1)#: compactflash card enable cf0_dir: compactflash data direction cf0_en#: compactflash buffer enable cf0_iois16#: compactflash i/o is 16 bits cf0_ready: compactflash ready cf0_reset: compactflash reset cf0_stschg#: compactflash status change cf0_vccen#: compactflash v cc enable cf1_cd(2:1)#: compactflash card detect cf1_ce(2:1)#: compactflash card enable cf1_dir: compactflash data direction cf1_en#: compactflash buffer enable cf1_ready: compactflash ready cf1_reset: compactflash reset cf1_stschg#: compactflash status change cf1_vccen#: compactflash v cc enable cke0: sdram clock enable cke1: syncflash memory clock enable clk48: usb clock input clksel(2:0): pipeline clock select clkx(2:1): clock input cts0#, cts1#, cts2#: 16550 clear to send d(31:0): data bus dak(1:0)#: dma acknowledge dbus32: rom data bus mode dcd0#, dcd2#: 16550 data carrier detect dclk: tft dot clock divmode(1:0): divide-by mode dqm(3:0): sdram byte enable drq(1:0)#: dma request dsr0#, dsr2#: 16550 data set ready dtr0#, dtr2#: 16550 data terminal ready enab: tft display enable flm: stn first line clock fpd(15:0): lcd display data frm: csi frame input gnd2: internal ground gnd3: i/o ground gndad: a/d and d/a converter ground gndo: oscillator ground gndp: pll ground gndtp: touch panel ground gndu: usb transceiver ground gpio(61:0): general-purpose i/o gpo(63:62): general-purpose output hsync: tft horizontal sync i.c.: internally connected iocs16#: i/o 16-bit bus sizing iord#: i/o read iordy: i/o ready iowr#: i/o write irdin: irda data input irdout: irda data output jtck: n-wire clock jtdi: n-wire data input jtdo: n-wire data output jtms: n-wire mode select jtrst#: n-wire reset kport(7:0): key scan input kscan(11:0): key scan output loclk: stn load clock lbe(3:0)#: system bus byte enable m: stn modulation clock memrd#: memory read memwr#: memory write mips16en: mips16 enable mpower: main power control nmi#: non maskable interrupt remark # indicates active low.
data sheet u16277ej1v0ds 7 pd30181a, 30181ay pin indentification (2/2) nwireen: n-wire enable pcs(4:0)#: programmable chip select power: power switch poweron: power on state pwm(2:0): pulse width modulation ras#: sdram row address strobe rmode#: n-wire reset mode select romcs#: chip select for rom rp#: syncflash memory reset/power-down rstsw#: reset switch rtcrst#: real-time clock reset rtcx(2:1): real-time clock input rts0#, rts1#, rts2#: 16550 data request to send rxd0, rxd1, rxd2: 16550 receive data sa10: sdram address 10-bit sclk: i 2 s continuous clock scl1, scl0: i 2 c clock sck: csi serial clock sda1, sda0: i 2 c data sdatain: ac97 serial codec data input sdataout: ac97 serial codec data output sdclk: sdram clock sdcs(3:2)#: syncflash memory chip select sdcs(1:0)#: sdram chip select sdi: i 2 s serial codec data input sdo: i 2 s serial codec data output shclk: stn shift clock si: csi data input so: csi data output sreset#: ac97 reset sync: ac97 synchronous clock sysdir: system data direction sysen#: system data enable tc(1:0)#: terminal counter tpx(1:0): touch panel x coordinate data tpy(1:0): touch panel y coordinate data txd0, txd1, txd2: 16550 transmit data ube#: upper byte enable for system bus udn: usb function negative data udp: usb function positive data uhdn: usb host negative data uhdp: usb host positive data uoc: usb host root hub port over current upon: usb host root hub port power control vdd2: internal power supply vdd3: i/o power supply vddad: a/d and d/a converter power supply vddo: oscillator power supply vddp: pll power supply vddtp: touch panel power supply vddu: usb transceiver power supply vpbias: bias power control vplcd: logic power control vsync: tft vertical sync we#: sdram write enable ws: i 2 s word select remark # indicates active low.
data sheet u16277ej1v0ds 8 pd30181a, 30181ay internal block diagram and example of connection of external blocks cpu core internal block diagram lcd control debug i/f interrupt control serial (uart) 3ch pwm control 3ch key scan i/f watchdog timer rtc/ timer d/a a/d i 2 s control power management cpu i/f v r 4120 cpu core v r 4181a in-circuit emulator bus control 32/16-bit bus card/ide control 2 slots usb func. control dma usb host control ac97 control sdram/ syncflash rom/flash memory isa i/o devices mcu, codec control, etc. bluetooth tm baseband stereo codec hdd, cd-rom stn/tft lcd panel color/monochrome mouse printer pcm sound audio input battery monitor touch panel pc communication compactflash/ pc card sdram control buf buf serial (i 2 c) 2ch touch panel control analog control serial (csi) gpio 64 max. port control led lcd backlight contrast 32.768 khz 18.432 mhz n-wire irda/ rs-232-c driver, bluetooth baseband, etc. ccd module, serial eeprom tm etc. bridge bridge clock generator virtual address bus internal data bus control (o) control (i) address/data (o) address/data (i) bus interface data cache (8 kb) instruction cache (8 kb) tlb cp0 cpu clock generator internal clock
data sheet u16277ej1v0ds 9 pd30181a, 30181ay contents 1. pin functions ............................................................................................................... ................... 10 1.1 pin functions ............................................................................................................... .......................... 10 1.2 pin status in specific status ............................................................................................... ................. 26 1.3 pin i/o circuit types and recommended connection of unused pins............................................ 33 1.4 pin i/o circuits ............................................................................................................ ........................... 36 2. electrical specifications ................................................................................................... ..... 37 3. package drawing ............................................................................................................. ............. 68 4. recommended soldering conditions .................................................................................. 69
data sheet u16277ej1v0ds 10 pd30181a, 30181ay 1. pin functions remark # indicates active low. 1.1 pin functions (1) system bus interface signals (1/3) signal name i/o function alternate function a24 o cke1 a23 o rp# a(22:15) o address bus these pins are used to specify system bus addresses. they are used to access rom, flash memory, sram, isa devices, pc cards, ide (ata) devices, and general-purpose devices. gpio(61:54) sa10 o address bit 10 for sdram or syncflash memory instead of connecting to a10, connect this pin (sa10) to address bit 10 in sdram or syncflash memory. ? a(14:0) o address bus these pins are used to specify system bus addresses. they are used to access sdram, syncflash memory, rom, flash memory, sram, isa devices, compactflash/pc cards, ide (ata) devices, and general-purpose devices. ? d(31:0) i/o data bus these pins are used to transfer data to the v r 4181a and sdram, syncflash memory, rom, flash memory, sram, isa devices, compactflash/pc cards, ide (ata) devices, and general-purpose devices. ? pcs(4:0)# o programmable chip select these pins can be set as active when the v r 4181a accesses rom, flash memory, sram, and general-purpose devices. they can be connected only to devices that are not subject to bus sizing via the iocs16# pin. ? romcs# o boot rom chip select this pin can be set as active when the v r 4181a accesses boot rom or flash memory. when the bmode(1:0) pin status is 01 and the rtcrst# signal has been cleared, the v r 4181a fetches the boot code from a device connected to the romcs# pin to activate this pin. ? memrd# o system bus memory read this pin becomes active when the v r 4181a reads data from any of the following devices. ? rom, flash memory, sram, or general-purpose devices controlled by the romcs# pin or pcs# pin ? external isa bus memory space devices and compactflash/pc card memory space devices ?
data sheet u16277ej1v0ds 11 pd30181a, 30181ay (2/3) signal name i/o function alternate function memwr# o system bus memory write this pin becomes active when the v r 4181a writes to any of the following devices. ? rom, flash memory, sram, or general-purpose devices controlled by the romcs# pin or pcs# pin ? external isa bus memory space devices and compactflash/pc card memory space devices ? iord# o system bus i/o read this pin becomes active when the v r 4181a reads data from the external isa bus i/o space devices or compactflash/pc card i/o ports. it is valid only when accessing the external isa bus i/o space. ? iowr# o system bus i/o write this pin becomes active when the v r 4181a writes data to external isa bus i/o space devices or compactflash/pc card i/o ports. it is valid only when accessing the external isa bus i/o space. ? iordy i system bus i/o channel ready this pin (iordy) is set as inactive in relation to read/write strobes from the v r 4181a in order to extend the access time for a device connected to the system bus. it is set as active once the device is in a m ode that supports access from the v r 4181a. it can be used to access a device connected to the romcs# pin or pcs# pin or a device connected to the external isa space. ? iocs16# i system bus sizing request set this signal as active when an isa device connected to the system bus accesses data in 16-bit width. bus sizing that uses this pin iocs16# is enabled only when accessing the external isa space. ? ube# o system bus higher byte enable this pin becomes active during system bus access if the hi gher bytes of the 16-bit data bus are valid. it can be used if a device connected to the romcs# or pcs# pin or a device connected to the external isa space uses 16-bit width. ? lbe(3:0)# o system bus byte enable the lbe(3:0)# signal pins used for 32-bit general-purpose devices are shared as the dqm(3:0) signal pins for sdram and syncflash memory, so the function of this pin changes based on time division. when the v r 4181a accesses a device that uses the romcs# pin or pcs# pin, the lbe(3:0)# signals become valid only when the sysen# signal is at low level. this signal indicates the data bus?s valid byte lane. if the device connected to the romcs# pin or pcs# pin has 32-bit width, this pin can be used. when the sysen# pin is at high level, this pin operates as the dqm(3:0) pins that are referenced by sdram. dqm(3:0)
data sheet u16277ej1v0ds 12 pd30181a, 30181ay (3/3) signal name i/o function alternate function sysdir note o data bus isolation buffer direction control this signal is valid only when accessing devices other than sdram or syncflash memory devices. the signal is at high level during read cycles and at low level during write cycles. ? sysen# note o enables data bus isolation buffer connection this signal is set to high level during sdram and syncflash memory cycles and is at low level when accessing any other devices. ? drq(1:0)# i dma service request signal the drq(1:0)# signals are sampled at the rising edge of tclock. be sure to hold this signal at active level until a dma request is acknowledged. set this signal as inactive when not using the drq(1:0)# signals. ? dak(1:0)# o enables dma service request this signal goes to active level when access to the target device occurs via dma transfer. ? tc(1:0)# i/o dma transfer completion signal (open drain) this signal is driven at active level when a dma transfer is completed. during a transfer, this signal operates as a dma stop request input signal. gpio(53:52) nmi# i non-maskable interrupt input this is an interrupt request signal that cannot be masked in relation to the cpu core. when the v r 4181a starts normally and the mpower signal is at high level, input from the nmi# pin is connected to the cpu core via the icu. while the mpower signal is at low level, input to the nmi# pin is monitored by the pmu as a source of nmi shutdowns. ? note the sysen# and sysdir signals are buffer control signals used to isolate the sdram and syncflash memory buses from other low-speed device buses. isolating high-speed memory access paths from other devices reduces the load on the system bus between the v r 4181a and the sdram or syncflash memory. when using the system bus isolation buffer, the correspondence between the sysen# and sysdir signals and the data bus isolation status is as shown below. sysen# sysdir bus operation 0 0 enables connection via data bus isolation buffer ? write cycle for rom, flash memory, sram, isa device, compactflash/pc card, or other general-purpose device ? hibernate mode 0 1 enables connection via data bus isolation buffer ? read cycle for rom, flash memory, sram, isa device, compactflash/pc card, or general-purpose device 1 0 disables connection via data bus isolation buffer read/write cycle for sdram or syncflash memory
data sheet u16277ej1v0ds 13 pd30181a, 30181ay (2) memory interface signals signal name i/o function alternate function sdclk o operating clock for sdram and syncflash memory this signal can also be set (via register settings) to stop clock output when not accessing sdram or syncflash memory. ? cke1 o operating clock enable signal for syncflash memory a24 cke0 o operating clock enable signal for sdram ? sdcs(3:2)# o chip select signal for syncflash memory ? sdcs(1:0)# o chip select signal for sdram ? ras# o row address strobe signal for sdram and syncflash memory ? cas# o column address strobe signal for sdram and syncflash memory ? dqm(3:0) o byte enable signal for sdram and syncflash memory the dqm(3:0) signals for sdram and syncflash memory shares pins with the lbe(3:0)# signals for 32-bit general-purpose devices, so the function of these pins change based on time division. when the sysen# signal is at high level, the pin operates as the dqm(3:0) signals which are referenced by sdram. lbe(3:0)# we# o write enable signal for sdram and syncflash memory ? rp# o syncflash memory initialization/power down signal a23
data sheet u16277ej1v0ds 14 pd30181a, 30181ay (3) initialization interface signals signal name i/o function alternate function power i v r 4181a activation request (power switch) signal when the rising edge of this signal is detected in hibernate mode, an activation factor occurs (the v r 4181a restores to fullspeed mode). ? rstsw# i v r 4181a reset signal this signal initializes the internal statuses of all resettable devices except the rtc timer, pmu, giu, and pwmu channels 0 and 1. ? rtcrst# i v r 4181a rtc reset signal this signal initializes the internal statuses of all resettable devices, including the rtc timer. when supplying power to a device for the first time, be sure to set this signal as active for external circuits. ? poweron o v r 4181a activation indication when an activation factor has been detected, this signal becomes active (high level) for a specified amount of time. ? mpower o v r 4181a operation in progress indication when 2.5 v circuits are operating, this signal becomes active (high level). in hibernate mode, it is inactive (low level). when this signal is inactive, the 2.5 v power supply can be stopped. ? remarks 1. activation factors are used to restore from hibernate mode to fullspeed mode. 2. for further description of the operation of initialization interface signals, see hardware user?s manual . (4) clock interface signals signal name i/o function alternate function rtcx(2:1) ? 32.768 khz crystal resonator connection pin ? clkx(2:1) ? 18.432 mhz crystal resonator connection pin ?
data sheet u16277ej1v0ds 15 pd30181a, 30181ay (5) lcd interface signals signal name i/o function alternate function dclk/shclk o dot clock (dclk) for tft/shift clock (shclk) for stn ? hsync/loclk o horizontal sync signal for tft/load clock for stn nwireen vsync/flm o vertical sync signal for tft/first line clock for stn bmode1 enab/m o display enable signal for tft/m clock for stn bmode0 fpd15 o lcd display data cf1_ready, gpio51 fpd14 o lcd display data cf1_stschg#, gpio50 fpd(13:12) o lcd display data cf1_ce(2:1)#, gpio(49:48) fpd(11:10) o lcd display data cf1_cd(2:1)#, gpio(47:46) fpd(9:4) o lcd display data gpio(45:40) fpd(3:0) o lcd display data ? vpbias o led bias power control this signal can be used as a general-purpose output when not using the lcd controller. gpo63 vplcd o lcd logic power control this signal can be used as a general-purpose output when not using the lcd controller. gpo62 caution the connection between the fpd(15:0) of the v r 4181a and lcd panel data line corresponds to the panel data width, as shown below. v r 4181a stn panel data (4 bits) stn panel data (8 bits) tft panel data (12 bits) tft panel data (16 bits) fpd0 data line 0 data line 0 data line (b0) data line (b0) fpd1 data line 1 data line 1 data line (b1) data line (b1) fpd2 data line 2 data line 2 data line (b2) data line (b2) fpd3 data line 3 data line 3 data line (b3) data line (b3) fpd4 ? data line 4 data line (g0) data line (b4) fpd5 ? data line 5 data line (g1) data line (g0) fpd6 ? data line 6 data line (g2) data line (g1) fpd7 ? data line 7 data line (g3) data line (g2) fpd8 ? ? data line (r0) data line (g3) fpd9 ? ? data line (r1) data line (g4) fpd10 ? ? data line (r2) data line (g5) fpd11 ? ? data line (r3) data line (r0) fpd12 ? ? ? data line (r1) fpd13 ? ? ? data line (r2) fpd14 ? ? ? data line (r3) fpd15 ? ? ? data line (r4)
data sheet u16277ej1v0ds 16 pd30181a, 30181ay (6) compactflash/pc card/ide (ata) interface signal signal name i/o function alternate function cf1_cd(2:1)# i compactflash/pc card (slot 1) detection signal fpd(11:10), gpio(47:46) cf1_ce(2:1)# o compactflash/pc card (slot 1) enable signal fpd(13:12), gpio(49:48) cf1_stschg# i compactflash/pc card (slot 1) status change signal fpd14, gpio50 cf1_ready i compactflash/pc card (slot 1) ready signal fpd15, gpio51 cf1_reset o compactflash/pc card (slot 1) reset signal dbus32 cf1_dir o compactflash/pc card (slot 1) data bus direction control signal kport4, gpio39 cf1_en# o compactflash/pc card (slot 1) buffer enable signal kport5, gpio38 cf1_vccen# o compactflash/pc card (slot 1) v cc enable signal kscan4, gpio37 cf0_cd(2:1)# i compactflash/pc card (slot 0) detection signal gpio(36:35) cf0_iois16# i compactflash/pc card (slot 0) i/o 16-bit bus signal gpio34 cf_wait# i compactflash/pc card (slots 0, 1) wait signal gpio33 cf0_ce(2:1)# o compactflash/pc card (slot 0) enable signal gpio(32:31) cf0_stschg# i compactflash/pc card (slot 0) status change signal gpio30 cf0_ready i compactflash/pc card (slot 0) ready signal gpio29 cf0_reset o compactflash/pc card (slot 0) reset signal gpio28 cf0_dir o compactflash/pc card (slot 0) data bus direction control signal gpio27 cf0_en# o compactflash/pc card (slot 0) buffer enable signal gpio26 cf_reg# o compactflash/pc card (slots 0, 1) register select signal gpio25 cf0_vccen# o compactflash/pc card (slot 0) v cc enable signal gpio24 cautions 1. be sure to use memrd#, memwr#, iord#, and iowr# respectively as compactflash/pc card access strobe signals oe#, we#, iord#, and iowr#. 2. the cf0_en#, cf1_en#, cf0_dir, and cf1_dir signals are used to control the buffer that isolates the compactflash/pc card?s bus from other device?s buses. this isolation of the compactflash/pc card?s bus enables hot plug-in support. the following table lists the correspondence between the cf0_en#, cf1_en#, cf0_dir, and cf1_dir signals and data bus isolation statuses when using the data bus isolation buffer. cf0_en#, cf1_en# cf0_dir, cf1_dir operation of bus 0 0 enable connection via data bus isolation buffer ? write cycle to compactflash/pc card 0 1 enable connection via data bus isolation buffer ? read cycle to compactflash/pc card 1 ? (undefined) disable connection via data bus isolation buffer
data sheet u16277ej1v0ds 17 pd30181a, 30181ay (7) usb (host/function) interface signals signal name i/o function alternate function clk48 i usb clock (48 mhz) ? uhdp i/o usb host serial data (+) signal be sure to connect a 22 ? resistor in series for impedance matching. ? uhdn i/o usb host serial data (?) signal be sure to connect a 22 ? resistor in series for impedance matching. ? upon o usb host route hub power control signal ? uoc i usb host route hub overcurrent input signal ? udp i/o usb function serial data (+) signal be sure to connect a 22 ? resistor in series for impedance matching. ? udn i/o usb function serial data (?) signal be sure to connect a 22 ? resistor in series for impedance matching. ? (8) ac97/i 2 s stereo audio interface signals signal name i/o function alternate function bitclk/sclk i/o bit clock input (12.288 mhz) for ac97/input or output of i 2 s clock (maximum frequency during input: 6.144 mhz). when used as the sclk signal, this signal is output by the v r 4181a when the i2su is in master mode and is input from an external source in slave mode. cts2# sync/ws i/o synchronous clock output for ac97/input or output of i 2 s word select signal when used as the ws signal, this signal is output by the v r 4181a when the i2su is in master mode and is input from an external source in slave mode. rts2#, divmode1 sdataout/sdo o serial data output signal for ac97/serial data output signal for i 2 s dtr2#, divmode0 sdatain/sdi i serial data input signal for ac97/serial data input signal for i 2 s dcd2# sreset# o reset signal for ac97 dsr2#
data sheet u16277ej1v0ds 18 pd30181a, 30181ay (9) clocked serial interface signals signal name i/o function alternate function sck i/o serial clock (maximum frequency for input and output: 4.6 mhz) this signal is output by the v r 4181a in master mode and is input from an external source in slave mode. kscan11, gpio23 si i serial data input signal kscan10, gpio22 so o serial data output signal this signal is set to high impedance when the value of the frmen bit and frmmd bit is 1 in the csimode register, and the frm signal is at high level. kscan9 , gpio21 frm i serial frame signal this signal determines the data direction (transmit/receive), or it can be used to enable (low level) or disable (high level) transfers. kscan8, gpio20
data sheet u16277ej1v0ds 19 pd30181a, 30181ay (10) 16550 (uart) serial interface signals signal name i/o function alternate function rxd0 i serial (channel 0) receive data ? txd0 o serial (channel 0) transmit data clksel2 rts0# o serial (channel 0) transmit request signal gpio19, clksel1 cts0# i serial (channel 0) transmit enable signal gpio18 dtr0#/rts1# o serial (channel 0) terminal ready signal/serial (channel 1) transmit request signal gpio17, clksel0 dcd0# i serial (channel 0) carrier detection signal gpio16 dsr0#/cts1# i serial (channel 0) data set ready signal/serial (channel 1) transmit enable signal gpio15 rxd1 i serial (channel 1) receive data scl1, gpio14 txd1 o serial (channel 1) transmit data sda1, gpio13 rxd2 i serial (channel 2) receive data irdin txd2 o serial (channel 2) transmit data irdout, mips16en rts2# o serial (channel 2) transmit request signal sync, ws, divmode1 cts2# i serial (channel 2) transmit enable signal bitclk, sclk dtr2# o serial (channel 2) terminal ready signal sdataout, sdo, divmode0 dcd2# i serial (channel 2) carrier detection signal sdatain, sdi dsr2# i serial (channel 2) data set ready signal sreset# (11) irda interface signals signal name i/o function alternate function irdin i irda receive data input rxd2 irdout o irda transmit data output txd2, mips16en (12) i 2 c serial interface signals ( pd30181ay only) signal name i/o function alternate function scl1 i/o serial clock (open drain) for i 2 c (channel 1) rxd1, gpio14 sda1 i/o serial i/o data (open drain) for i 2 c (channel 1) txd1, gpio13 scl0 i/o serial clock (open drain) for i 2 c (channel 0) kport7, gpio12 sda0 i/o serial i/o data (open drain) for i 2 c (channel 0) kport6, gpio11
data sheet u16277ej1v0ds 20 pd30181a, 30181ay (13) pwm interface signals signal name i/o function alternate function pwm2 o pwm output (channel 2) kscan5, gpio10 pwm1 o pwm output (channel 1) kscan6, gpio9 pwm0 o pwm output (channel 0) kscan7, gpio8 (14) keyboard interface signals signal name i/o function alternate function kport7 i key scan input data scl0, gpio12 kport6 i key scan input data sda0, gpio11 kport5 i key scan input data cf1_en#, gpio38 kport4 i key scan input data cf1_dir, gpio39 kport(3:0) i key scan input data gpio(7:4) kscan11 o key scan output data sck, gpio23 kscan10 o key scan output data si, gpio22 kscan9 o key scan output data so, gpio21 kscan8 o key scan output data frm, gpio20 kscan7 o key scan output data pwm0, gpio8 kscan6 o key scan output data pwm1, gpio9 kscan5 o key scan output data pwm2, gpio10 kscan4 o key scan output data cf1_vccen#, gpio37 kscan(3:0) o key scan output data gpio(3:0) (15) touch panel/analog interface signals signal name i/o function alternate function tpx(1:0) i/o touch panel x coordinate data this signal is used to detect the x coordinate of the touch panel location that has been pressed when the supply voltage is applied to the x coordinates and y coordinates. ? tpy(1:0) i/o touch panel y coordinate data this signal is used to detect the y coordinate of the touch panel location that has been pressed when the supply voltage is applied to the y coordinates and x coordinates. ? ain(3:0) i general-purpose a/d data input ? aout o general-purpose d/a data output ?
data sheet u16277ej1v0ds 21 pd30181a, 30181ay (16) debug interface signals signal name i/o function alternate function jtck i n-wire clock ? jtms i n-wire mode select signal this signal selects n-wire serial transfer mode. ? jtdi/rmode# i n-wire input data/n-wire reset mode select signal this pin functions alternately as rmode# and jtdi. when jtrst# is active it functions as rmode#, and when jtrst# is inactive it functions as jtdi. ? rmode# input when jtrst# is active, this pin is the reset mode pin. the initial value for a debug reset is determined by the level of this signal. a debug reset is a reset of the processor, and there are two types: a debug cold reset and a debug soft reset. this serves the same function as cold reset input and soft reset input from various target systems. 0: sets debug reset as valid and resets cpu core 1: sets debug reset as invalid and does not reset cpu core ? jtdi input when the jtrst# signal is inactive, this pin operates as the n-wire serial data input. ? jtdo o n-wire serial data output ? jtrst# i n-wire reset signal ? bktgio# i/o n-wire break trigger i/o ? bktgio#: when used for input setting when jtrst# is inactive and bktgio# is used for input setting, this pin is the event trigger/break request input pin. when break requests are valid, setting bktgio# to low level stops execution of user programs in normal mode and forcibly shifts the processor to debug mode. after bktgio# goes to low level in debug mode, break requests are retained until the processor is restored to normal mode. 0: requests break and forcibly shifts processor to debug mode 1: retains current status of processor ? bktgio#: when used for output setting when jtrst# is inactive and bktgio# is used for output setting, this pin is the event trigger/break output pin. when the processor is operating in normal mode and an event is detected that meets any of the conditions for a hardware breakpoint (instruction address breakpoint or data access breakpoint), an event trigger is output from bktgio# as a low level signal (one pulse) and detection of the event is reported to the external debugging tool. finally, after the event trigger is output, all detected events are reported as one event trigger. when the processor is shifted to debug mode, output continues at low level and all previously non-reported events are not reported. 0: hardware breakpoint was detected the processor is shifted to debug mode. 1: the processor is in normal mode. ?
data sheet u16277ej1v0ds 22 pd30181a, 30181ay (17) general-purpose i/o signals (1/2) signal name i/o function alternate function gpo63 o vpbias gpo62 o general-purpose output ports vplcd gpio(61:54) i/o a(22:15) gpio(53:52) i/o tc(1:0)# gpio51 i/o fpd15, cf1_ready gpio50 i/o fpd14, cf1_stschg# gpio(49:48) i/o fpd(13:12), cf1_ce(2:1)# gpio(47:46) i/o fpd(11:10), cf1_cd(2:1)# gpio(45:40) i/o fpd(9:4) gpio39 i/o cf1_dir, kport4 gpio38 i/o cf1_en#, kport5 gpio37 i/o cf1_vccen#, kscan4 gpio(36:35) i/o cf0_cd(2:1)# gpio34 i/o cf0_iois16# gpio33 i/o cf_wait# gpio(32:31) i/o cf0_ce(2:1)# gpio30 i/o cf0_stschg# gpio29 i/o cf0_ready gpio28 i/o cf0_reset gpio27 i/o cf0_dir gpio26 i/o cf0_en# gpio25 i/o cf_reg# gpio24 i/o cf0_vccen# gpio23 i/o sck, kscan11 gpio22 i/o si, kscan10 gpio21 i/o so, kscan9 gpio20 i/o frm, kscan8 gpio19 i/o rts0#/ clksel1 gpio18 i/o general-purpose i/o ports cts0#
data sheet u16277ej1v0ds 23 pd30181a, 30181ay (2/2) signal name i/o function alternate function gpio17 i/o dtr0#, rts1#, clksel0 gpio16 i/o dcd0# gpio15 i/o dsr0#, cts1# gpio14 i/o rxd1, scl1 gpio13 i/o txd1, sda1 gpio12 i/o scl0, kport7 gpio11 i/o sda0, kport6 gpio10 i/o pwm2, kscan5 gpio9 i/o pwm1, kscan6 gpio8 i/o pwm0, kscan7 gpio(7:4) i/o kport(3:0) gpio(3:0) i/o general-purpose i/o ports kscan(3:0)
data sheet u16277ej1v0ds 24 pd30181a, 30181ay (18) mode setting signals these signals are used to set various modes. these signals are sampled only when the rtcrst# signal has changed to high level. at all other times, they can be used as alternate-function pins. in order to disconnect a pull-up or pull-down resistor for mode setting during normal operation, use a switch linked to the rtcrst# signal. signal name i/o function alternate function bmode1 i vsync, flm bmode0 i boot rom type setting bmode(1:0) = 01: rom/flash memory bmode(1:0) = 10: syncflash memory bmode(1:0) = 00 or 11: setting prohibited enab, m nwireen i n-wire use enable signal 0: disabled 1: enabled hsync, loclk dbus32 i boot rom bus width specification 0: 16 bits 1: 32 bits cf1_reset clksel2 i txd0 clksel1 i rts0#, gpio19 clksel0 i set frequency of cpu core?s pipeline reference clock (aclock) clksel(2:0) = 111: setting prohibited (147.4 mhz) clksel(2:0) = 110: 131.1 mhz clksel(2:0) = 101: 118.0 mhz clksel(2:0) = 100: 98.3 mhz clksel(2:0) = 011: 90.7 mhz clksel(2:0) = 010: 84.1 mhz clksel(2:0) = 001: 78.5 mhz clksel(2:0) = 000: 73.7 mhz dtr0#, rts1#, gpio17 divmode1 i rts2#, sync, ws divmode0 i set division ratio of aclock and internal system bus reference clock (tclock) divmode(1:0) = 10: aclock/2 (div2 mode) divmode(1:0) = 01: aclock/3 (div3 mode) divmode(1:0) = 11, 00: setting prohibited dtr2#, sdo, sdataout mips16en i enables use of mips16 instruction set 0: use disabled 1: use enabled txd2, irdout
data sheet u16277ej1v0ds 25 pd30181a, 30181ay (19) dedicated v dd /gnd signals signal name power supply function vdd2 2.5 v power supply for internal logic gnd2 2.5 v gnd for internal logic vdd3 3.3 v power supply for i/o buffers (except for i/o buffer of usb transceiver) gnd3 3.3 v gnd for i/o buffers (except for i/o buffer of usb transceiver) vddu 3.3 v dedicated power supply for usb transceiver gndu 3.3 v dedicated gnd for usb transceiver vddp 2.5 v dedicated power supply for pll (analog unit) gndp 2.5 v dedicated gnd for pll (analog unit) vddo 3.3 v dedicated power supply for oscillator gndo 3.3 v dedicated gnd for oscillator vddad 3.3 v dedicated power supply for the a/d and d/a converters. the voltage applied to this pin becomes the maximum voltage value for the a/d and d/a converters? interface signals. gndad 3.3 v dedicated gnd for the a/d and d/a converters. the voltage applied to this pin becomes the minimum voltage value for the a/d and d/a converters? interface signals. vddtp 3.3 v dedicated power supply for touch panel interface gndtp 3.3 v dedicated gnd for touch panel interface caution the v r 4181a includes two power supply systems, a 2.5 v system and a 3.3 v system. when applying a voltage, be sure to apply it to the 3.3 v power supply system first. apply voltage to the 2.5 v power supply system according to the status of the mpower pin.
data sheet u16277ej1v0ds 26 pd30181a, 30181ay 1.2 pin statuses in specific status (1/7) pin name (signal name) alternate- function pin name (alternate signal name) during rtc reset after rtc reset after reset by rstsw or watchdog timer in suspend mode in hibernate mode or during shutdown by haltimer a24 cke1 0 0 0 note 1 0 a23 rp# 0 0 0 note 1 0 a(22:15) gpio(61:54) 0 0 0 note 1 0 a(14:0) ?000 note 1 0 sa10 ?000 note 1 0 d(31:0) ?000 note 1 0 iord# ? hi-z hi-z 1 note 1 hi-z iowr# ? hi-z hi-z 1 note 1 hi-z iordy ? hi-z hi-z ? ? hi-z iocs16# ? hi-z hi-z ? ? hi-z ube# ? 0 0 1/0 note 1 0 pcs(4:0)# ? hi-z hi-z 1 note 1 hi-z sysdir ?000 note 1 0 sysen# ? 0 0 1/0 note 1 0 drq(1:0)# ? hi-z hi-z ? ? hi-z dak(1:0)# ? hi-z hi-z 1 note 1 hi-z tc(1:0)# gpio(53:52) hi-z hi-z ? note 1 hi-z nmi# ?????? romcs# ? hi-z hi-z 1 note 1 hi-z memrd# ? hi-z hi-z 1 note 1 hi-z memwr# ? hi-z hi-z 1 note 1 hi-z rp#a23 001 note 1 0 sdclk ? 0 operating operating 0 0 cke1 a24 0 1 1 note 1 0 cke0 ? 0 1 note 2 00 sdcs(3:2)# ? 0 1 1/0 1/0 0 sdcs(1:0)# ? 0 1 1/0 1/0 0 ras# ? 0 1 1/0 1/0 0 notes 1. the status in the previous fullspeed mode is retained. 2. changes according to the setting in the sdramact register in the giu. when sdact bit = 0: 1 when sdact bit = 1: 0 remarks 1. 0: low level, 1: high level, hi-z: high impedance 2. when a pin has high impedance, the buffer?s input enable setting is off. leakage current will not occur even when an intermediate level is applied.
data sheet u16277ej1v0ds 27 pd30181a, 30181ay (2/7) pin name (signal name) alternate- function pin name (alternate signal name) during rtc reset after rtc reset after reset by rstsw or watchdog timer in suspend mode in hibernate mode or during shutdown by haltimer cas# ? 0 1 1/0 1/0 0 dqm(3:0), lbe(3:0)# ?001/01/00 we# ?011/01/00 power ?????? rstsw#?????? rtcrst#?????? poweron?00000 mpower?00110 rtcx(2:1)?????? clkx(2:1)?????? dclk, shclk?000 note 1 0 hsync, loclk nwireen note 2 00 note 1 0 vsync, flm bmode1 note 3 00 note 1 0 enab, m bmode0 note 3 00 note 1 0 fpd15 cf1_ready, gpio51 hi-z hi-z 0 note 1 hi-z fpd14 cf1_stschg#, gpio50 hi-z hi-z 0 note 1 hi-z fpd(13:12) cf1_ce(2:1)#, gpio(49:48) hi-z hi-z 0 note 1 hi-z fpd(11:10) cf1_cd(2:1)#, gpio(47:46) hi-z hi-z 0 note 1 hi-z fpd(9:4) gpio(45:40) hi-z hi-z 0 note 1 0 fpd(3:0)?000 note 1 0 vplcd gpo62 hi-z hi-z hi-z hi-z hi-z vpbias gpo63 hi-z hi-z hi-z hi-z hi-z notes 1. the status in the previous fullspeed mode is retained. if the lcd panel?s voltage drops during suspend mode, enter settings in the lcu register to stop output operations and set the pin?s value to 0. 2. the input level is sampled when the rtcrst# signal has changed to high level in order to enable or disable use of the n-wire. 3. the input level is sampled when the rtcrst# signal has changed to high level in order to set the boot rom type. remarks 1. 0: low level, 1: high level, hi-z: high impedance 2. when a pin has high impedance, the buffer?s input enable setting is off. leakage current will not occur even when an intermediate level is applied.
data sheet u16277ej1v0ds 28 pd30181a, 30181ay (3/7) pin name (signal name) alternate- function pin name (alternate signal name) during rtc reset after rtc reset after reset by rstsw or watchdog timer in suspend mode in hibernate mode or during shutdown by haltimer cf1_cd(2:1)# fpd(11:10), gpio(47:46) hi-z hi-z ? ? hi-z cf1_ce(2:1)# fpd(13:12) , gpio(49:48) hi-z hi-z hi-z note 1 hi-z cf1_stschg# fpd14, gpio50 hi-z hi-z ? ? hi-z cf1_ready fpd15, gpio51 hi-z hi-z ? ? hi-z cf1_reset dbus32 note 2 hi-z hi-z note 1 note 3 cf1_dir kport4, gpio39 hi-z hi-z 0 note 1 hi-z cf1_en# kport5, gpio38 hi-z hi-z hi-z note 1 hi-z cf1_vccen# kscan4, gpio37 hi-z hi-z 1 note 1 hi-z cf0_cd(2:1)# gpio(36:35) hi-z hi-z ? ? hi-z cf0_iois16# gpio34 hi-z hi-z ? ? hi-z cf_wait# gpio33 hi-z hi-z ? ? hi-z cf0_ce(2:1)# gpio(32:31) hi-z hi-z hi-z note 1 hi-z cf0_stschg# gpio30 hi-z hi-z ? ? hi-z cf0_ready gpio29 hi-z hi-z ? ? ? cf0_reset gpio28 hi-z hi-z hi-z note 1 hi-z cf0_dir gpio27 hi-z hi-z 0 note 1 hi-z cf0_en# gpio26 hi-z hi-z hi-z note 1 hi-z cf_reg# gpio25 hi-z hi-z hi-z note 1 hi-z cf0_vccen# gpio24 hi-z hi-z 1 note 1 hi-z clk48 ? hi-z hi-z note 3 note 3 hi-z uhdp ? hi-z hi-z hi-z hi-z hi-z uhdn ? hi-z hi-z hi-z hi-z hi-z upon ?00000 uoc ? hi-z hi-z hi-z hi-z hi-z udp ? hi-z hi-z hi-z hi-z hi-z notes 1. the status in the previous fullspeed mode is retained. 2. the input level is sampled when the rtcrst# signal has changed to high level in order to set the boot rom bus width. 3. the registers in the giu can be used to set 1, 0, or high impedance. remarks 1. 0: low level, 1: high level, hi-z: high impedance 2. when a pin has high impedance, the buffer?s input enable setting is off. leakage current will not occur even when an intermediate level is applied.
data sheet u16277ej1v0ds 29 pd30181a, 30181ay (4/7) pin name (signal name) alternate- function pin name (alternate signal name) during rtc reset after rtc reset after reset by rstsw or watchdog timer in suspend mode in hibernate mode or during shutdown by haltimer udn ? hi-z hi-z hi-z hi-z hi-z bitclk sclk, cts2# hi-z hi-z hi-z hi-z hi-z sync ws, rts2#, divmode1 note 1 hi-z hi-z hi-z hi-z sdataout sdo, dtr2#, divmode0 note 1 hi-z hi-z hi-z hi-z sdatain sdi, dcd2# hi-z hi-z hi-z hi-z hi-z sreset# dsr2# hi-z hi-z hi-z hi-z hi-z sclk bitclk, cts2# hi-z hi-z hi-z hi-z hi-z ws sync, rts2#, divmode1 note 1 hi-z hi-z hi-z hi-z sdo sdataout, dtr2#, divmode0 note 1 hi-z hi-z hi-z hi-z sdi sdatain, dcd2# hi-z hi-z hi-z hi-z hi-z sck kscan11, gpio23 hi-z hi-z hi-z note 2 hi-z si kscan10, gpio22 hi-z hi-z hi-z note 2 hi-z so kscan9, gpio21 hi-z hi-z hi-z note 2 hi-z frm kscan8, gpio20 hi-z hi-z ? note 2 hi-z rxd0 ? hi-z hi-z ? ? hi-z txd0 clksel2 note 3 hi-z 1 note 2 1 rts0# gpio19, clksel1 note 3 hi-z 1 note 2 1 cts0# gpio18 hi-z hi-z ? ? hi-z notes 1. the input level is sampled when the rtcrst# signal has changed to high level in order to set the division ratio for the cpu core?s pipeline reference clock (aclock) and the peripheral system bus?s reference clock (tclock). 2. the status in the previous fullspeed mode is retained. 3. the input level is sampled when the rtcrst# signal has changed to high level in order to set the frequency of the cpu core?s pipeline reference clock (aclock). remarks 1. 0: low level, 1: high level, hi-z: high impedance 2. when a pin has high impedance, the buffer?s input enable setting is off. leakage current will not occur even when an intermediate level is applied.
data sheet u16277ej1v0ds 30 pd30181a, 30181ay (5/7) pin name (signal name) alternate- function pin name (alternate signal name) during rtc reset after rtc reset after reset by rstsw or watchdog timer in suspend mode in hibernate mode or during shutdown by haltimer dtr0# rts1#, gpio17, clksel0 note 1 hi-z 1 note 2 hi-z dcd0# gpio16 ? ? ? ? ? dsr0# cts1#, gpio15 ? ? ? ? hi-z rxd1 scl1, gpio14 hi-z hi-z ?? hi-z txd1 sda1, gpio13 hi-z hi-z 1 note 2 hi-z rts1# dtr0#, gpio17, clksel0 note 1 hi-z 1 note 2 hi-z cts1# dsr0#, gpio15 ? ? ? ? hi-z rxd2 irdin hi-z hi-z hi-z hi-z hi-z txd2 irdout, mips16en note 3 hi-z 1 note 2 hi-z rts2# sync, ws, divmode1 note 4 hi-z 1 note 2 hi-z cts2# sclk, bitclk hi-z hi-z hi-z ? hi-z dtr2# sdo, sdataout, divmode0 note 4 hi-z 1 note 2 hi-z dcd2# sdi, sdatain hi-z hi-z hi-z ? hi-z dsr2# sreset# hi-z hi-z hi-z ? hi-z irdin rxd2 hi-z hi-z hi-z hi-z hi-z irdout txd2, mips16en note 3 hi-z 0 note 2 hi-z notes 1. the input level is sampled when the rtcrst# signal has changed to high level in order to set the frequency of the cpu core?s pipeline reference clock (aclock). 2. the status in the previous fullspeed mode is retained. 3. the input level is sampled when the rtcrst# signal has changed to high level in order to set whether to use the mips16 instruction set or not. 4. the input level is sampled when the rtcrst# signal has changed to high level in order to set the division ratio for the cpu core?s pipeline reference clock (aclock) and the peripheral system bus?s reference clock (tclock). remarks 1. 0: low level, 1: high level, hi-z: high impedance 2. when a pin has high impedance, the buffer?s input enable setting is off. leakage current will not occur even when an intermediate level is applied.
data sheet u16277ej1v0ds 31 pd30181a, 30181ay (6/7) pin name (signal name) alternate- function pin name (alternate signal name) during rtc reset after rtc reset after reset by rstsw or watchdog timer in suspend mode in hibernate mode or during shutdown by haltimer scl1 note 1 rxd1, gpio14 hi-z hi-z hi-z note 2 hi-z sda1 note 1 txd1, gpio13 hi-z hi-z hi-z note 2 hi-z scl0 note 1 kport7, gpio12 hi-z hi-z hi-z note 2 hi-z sda0 note 1 kport6, gpio11 hi-z hi-z hi-z note 2 hi-z pwm2 kscan5, gpio10 hi-z hi-z 0 note 2 hi-z pwm1 kscan6, gpio9 hi-z hi-z note 2 note 2 note 2 pwm0 kscan7, gpio8 hi-z hi-z note 2 note 2 note 2 kport7 scl0, gpio12 hi-z hi-z ? ? hi-z kport6 sda0, gpio11 hi-z hi-z ? ? hi-z kport5 cf1_en#, gpio38 hi-z hi-z ? ? hi-z kport4 cf1_dir, gpio39 hi-z hi-z ? ? hi-z kport(3:0) gpio(7:4) hi-z hi-z ? ? hi-z kscan11 sck, gpio23 hi-z hi-z 0 note 2 hi-z kscan10 si, gpio22 hi-z hi-z 0 note 2 hi-z kscan9 so, gpio21 hi-z hi-z 0 note 2 hi-z kscan8 frm, gpio20 hi-z hi-z 0 note 2 hi-z kscan7 pwm0, gpio8 hi-z hi-z 0 note 2 hi-z kscan6 pwm1, gpio9 hi-z hi-z 0 note 2 hi-z kscan5 pwm2, gpio10 hi-z hi-z 0 note 2 hi-z kscan4 cf1_vccen#, gpio37 hi-z hi-z 0 note 2 hi-z kscan(3:0) gpio(3:0) hi-z hi-z 0 note 2 hi-z tpx(1:0)?111 note 2 1 tpy(1:0) ? hi-z hi-z hi-z note 2 hi-z ain(3:0) ?????? aout ?000 note 2 0 notes 1. pd30181ay only 2. the status in the previous fullspeed mode is retained. remarks 1. 0: low level, 1: high level, hi-z: high impedance 2. when a pin has high impedance, the buffer?s input enable setting is off. leakage current will not occur even when an intermediate level is applied.
data sheet u16277ej1v0ds 32 pd30181a, 30181ay (7/7) pin name (signal name) alternate- function pin name (alternate signal name) during rtc reset after rtc reset after reset by rstsw or watchdog timer in suspend mode in hibernate mode or during shutdown by haltimer jtck note 1 ? hi-z hi-z hi-z hi-z hi-z jtms note 1 ? hi-z hi-z hi-z hi-z hi-z jtdi note 1 , rmode# ? hi-z hi-z hi-z hi-z hi-z jtdo note 1 ? hi-z hi-z hi-z hi-z hi-z jtrst# note 1 ? hi-z hi-z hi-z hi-z hi-z bktgio# note 1 ? hi-z hi-z hi-z hi-z hi-z gpo63 vpbias hi-z hi-z hi-z hi-z hi-z gpo62 vplcd hi-z hi-z hi-z hi-z hi-z gpio(61:54) note 2 a(22:15) hi-z hi-z note 3 note 3 note 3 gpio(53:0) note 4 hi-z note 5 hi-z note 3 note 3 note 3 notes 1. this is the pin status when the n-wire function has been set to use prohibit status via a setting for the nwireen pin. 2. when syncflash memory has been selected as the boot rom, this pin can be used as the gpio pin. 3. the registers in the giu can be used to set 1, 0, or high impedance. 4. see the other pin names and alternate-function pin names. 5. the gpio19 and gpio17 signals are sampled as clksel(1:0) when the rtcrst# signal has changed to high level in order to set the frequency of the cpu core?s pipeline reference clock (aclock). caution after an rtc reset, the gpio pins are set in the input direction and input disable status is set. input enable status can be set by software after an rtc reset. accordingly, there is no need to externally add elements such as pull-up or pull-down resistors for unused gpio pins in order to determine the signal status. however, gpio(61:54), which are shared with a(22:15), function as gpio pins only when syncflash memory has been selected. the status of output pins in hibernate mode can be specified by using software to enter the required settings in internal registers in advance. remarks 1. 0: low level, 1: high level, hi-z: high impedance 2. when a pin has high impedance, the buffer?s input enable setting is off. leakage current will not occur even when an intermediate level is applied.
data sheet u16277ej1v0ds 33 pd30181a, 30181ay 1.3 pin i/o circuit types and recommended connection of unused pins (1/3) pin name i/o i/o circuit type recommended connection of unused pins a24/cke1 o a leave open a23/rp# o a leave open a(22:15)/gpio(61:54) i/o a leave open a(14:0) o a leave open sa10 o a leave open d(31:0) i/o a connect to vdd3 or gnd3 via a resistor iord# o a leave open iowr# o a leave open iordy i a connect to vdd3 iocs16# i a connect to vdd3 ube# o a leave open pcs(4:0)# o a leave open sysdir o a leave open sysen# o a leave open drq(1:0)# i a connect to vdd3 dak(1:0)# o a leave open tc(1:0)#/gpio(53:52) i/o a leave open nmi# i a connect to vdd3 romcs# o a leave open memrd# o a leave open memwr# o a leave open sdclk o a leave open cke0 o a leave open sdcs(3:0)# o a leave open ras# o a leave open cas# o a leave open dqm(3:0)/lbe(3:0)# o a leave open we# o a leave open power i b connect to vdd3 rstsw# i b connect to vdd3 rtcrst# i b ? poweron o a leave open mpower o a leave open dclk/shclk o a leave open hsync/loclk/nwireen note i/o a connect to vdd3 or gnd3 via a resistor vsync/flm/bmode1 note i/o a connect to vdd3 or gnd3 via a resistor note the signal level is sampled when the rtcrst# signal has changed to high level.
data sheet u16277ej1v0ds 34 pd30181a, 30181ay (2/3) pin name i/o i/o circuit type recommended connection of unused pins enab/m/bmode0 note i/o a connect to vdd3 or gnd3 via a resistor fpd15/cf1_ready/gpio51 i/o a leave open fpd14/cf1_stschg#/gpio50 i/o a leave open fpd(13:12)/cf1_ce(2:1)#/gpio(49:48) i/o a leave open fpd(11:10)/cf1_cd(2:1)#/gpio(47:46) i/o a leave open fpd(9:4)/gpio(45:40) i/o a leave open fpd(3:0) o a leave open vplcd/gpo62 o a leave open vpbias/gpo63 o a leave open cf1_reset/dbus32 note i/o b connect to vdd3 or gnd3 via a resistor cf1_dir/kport4/gpio39 i/o b leave open cf1_en#/kport5/gpio38 i/o b leave open cf1_vccen#/kscan4/gpio37 i/o b leave open cf0_cd(2:1)#/gpio(36:35) i/o b leave open cf0_iois16#/gpio34 i/o b leave open cf_wait#/gpio33 i/o b leave open cf0_ce(2:1)#/gpio(32:31) i/o b leave open cf0_stschg#/gpio30 i/o b leave open cf0_ready/gpio29 i/o b leave open cf0_reset/gpio28 i/o b leave open cf0_dir/gpio27 i/o b leave open cf0_en#/gpio26 i/o b leave open cf_reg#/gpio25 i/o b leave open cf0_vccen#/gpio24 i/o b leave open sck/kscan11/gpio23 i/o b leave open si/kscan10/gpio22 i/o b leave open so/kscan9/gpio21 i/o b leave open frm/kscan8/gpio20 i/o b leave open rxd2/irdin i b leave open txd2/irdout/mips16en note i/o b connect to vdd3 or gnd3 via a resistor rts2#/sync/ws/divmode1 note i/o b connect to vdd3 or gnd3 via a resistor cts2#/bitclk/sclk i/o b leave open dtr2#/sdataout/sdo/divmode0 note i/o b connect to vdd3 or gnd3 via a resistor dcd2#/sdatain/sdi i b leave open dsr2#/sreset# i/o b leave open rxd0 i b connect to vdd3 txd0/clksel2 note i/o b connect to vdd3 or gnd3 via a resistor rts0#/gpio19/clksel1 note i/o b connect to vdd3 or gnd3 via a resistor note the signal level is sampled when the rtcrst# signal has changed to high level.
data sheet u16277ej1v0ds 35 pd30181a, 30181ay (3/3) pin name i/o i/o circuit type recommended connection of unused pins cts0#/gpio18 i/o b leave open dtr0#/rts1#/gpio17/clksel0 note i/o b connect to vdd3 or gnd3 via a resistor dcd0#/gpio16 i/o b leave open dsr0#/cts1#/gpio15 i/o b leave open rxd1/scl1/gpio14 i/o b leave open txd1/sda1/gpio13 i/o b leave open scl0/kport7/gpio12 i/o b leave open sda0/kport6/gpio11 i/o b leave open pwm2/kscan5/gpio10 i/o b leave open pwm1/kscan6/gpio9 i/o b leave open pwm0/kscan7/gpio8 i/o b leave open kport(3:0)/gpio(7:4) i/o b leave open kscan(3:0)/gpio(3:0) i/o b leave open clk48 i a leave open uhdp i/o g leave open uhdn i/o g leave open upon o a leave open uoc i b connect to gnd3 udp i/o g leave open udn i/o g leave open tpx(1:0) i/o c leave open tpy0 i/o c leave open tpy1 i/o d leave open ain(3:0) i e leave open aout o f leave open jtck i a leave open jtms i a leave open jtdi/rmode# i a leave open jtdo o a leave open jtrst# i a leave open bktgio# i/o a leave open note the signal level is sampled when the rtcrst# signal has changed to high level.
data sheet u16277ej1v0ds 36 pd30181a, 30181ay 1.4 pin i/o circuits type a p-ch in/out data output disable input enable vdd3 n-ch type d input enable p-ch in/out data output disable vddtp n-ch n-ch p-ch v ref n-ch + ? type b p-ch in/out data output disable open drain input enable vdd3 n-ch type e in p-ch v ref n-ch + ? type f analog output voltage out type c p-ch in/out data output disable vddtp n-ch p-ch v ref n-ch + ? type g + ? data output disable input enable ? in/out +in/out remark type a: low slew-rate output type b: schmitt-triggered input, low slew-rate output type g: differential i/o
data sheet u16277ej1v0ds 37 pd30181a, 30181ay 2. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit v dd25 2.5 v (vdd2, vddp pins) ?0.5 to +3.6 v supply voltage v dd33 3.3 v (vdd3, vddu, vddtp, vddad, vddo pins) ?0.5 to +4.0 v v dd33 3.7 v ?0.5 to +4.0 v input voltage v i v dd33 < 3.7 v ?0.5 to v dd33 + 0.3 v storage temperature t stg ?65 to +125 c cautions 1. do not short-circuit two or more output pins simultaneously. 2. if even one of the above parameters exceeds the absolute maximum ratings even momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, specify the value exceeding which the product may be physically damaged. use the product well within these ratings. the specifications and conditions shown in dc characteristics and ac characteristics are the ranges for normal operation and quality assurance of the product. 3. v i can be ? 1.5 v if the input pulse is less than 10 ns. operating conditions parameter symbol condition min. max. unit v dd25 2.5 v (vdd2, vddp pins) 2.3 2.7 v supply voltage v dd33 3.3 v (vdd3, vddu, vddtp, vddad, vddo pins) 3.0 3.6 v ambient temperature t a when operating at 131.1 mhz ?40 +85 c oscillation start voltage note 1 v dds 3.0 v oscillation hold voltage note 2 v ddh1 2.5 v oscillation hold voltage note 3 v ddh2 3.0 v notes 1. this is a voltage at which oscillation is always started after power application, and is applied to oscillators of 32.768 khz and 18.432 mhz. 2. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 32.768 khz. 3. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 18.432 mhz. remark the v r 4181a has two types of power supplies. the 3.3 v power supply should be turned on at first. turn on/off the 2.5 v power supply depending on the status of the mpower pin. capacitance (t a = ? 40 to +85 c, v dd33 = 0 v) parameter symbol condition min. max. unit input capacitance c i 10 pf i/o capacitance note 1 c i_usb 20 pf i/o capacitance note 2 c io unmeasured pins returned to 0 v. 10 pf notes 1. applies to the uhdp, uhdn, udp, and udn pins. 2. applies to i/o pins other than the uhdp, uhdn, udp, and udn pins.
data sheet u16277ej1v0ds 38 pd30181a, 30181ay dc characteristics (t a = ?40 to +85 c, v dd25 = 2.3 to 2.7 v, v dd33 = 3.0 to 3.6 v) (1) pins of i/o circuit types a, c, and d parameter symbol conditions min. typ. max. unit output voltage, high v oh pins of types a note 1 , c note 2 , and d note 3 , i oh = ? 2 ma 0.8v dd33 v output voltage, low v ol pins of types a note 1 , c note 2 , and d note 3 , i ol = 2 ma 0.4 v v ih pins of types a note 1 (excluding gpio pin of edge triggered interrupt), c note 2 , and d note 3 2.0 v dd33 + 0.3 v input voltage, high v ih1e pins of type a note 4 (gpio pin of edge triggered interrupt) 0.75v dd33 v dd33 + 0.3 v v il pins of type a note 1 (excluding gpio pin of edge triggered interrupt), c note 2 , and d note 3 ? 0.3 0.25v dd33 v input voltage, low v il1e pins of type a note 4 (gpio pin of edge triggered interrupt) ? 0.3 0.5 v notes 1. applies to the following pins. d(31:0), iordy, iocs16#, drq(1:0)#, tc(1:0)#/gpio(53:52), nmi#, hsync/loclk/nwireen, enab/m/bmode0, vsync/flm/bmode1, fpd15/cf1_ready/gpio51, fpd14/cf1_stschg#/gpio50, fpd(13:12)/cf1_ce(2:1)#/gpio(49:48), fpd(11:10)/cf1_cd(2:1)#/gpio(47:46), fpd(9:4)/gpio(45:40), clk48, jtck, jtms, jtdi/rmode#, jtrst#, bktgio#, a(14:0), a23/rp#, a24/cke1, cas#, cke0, dak(1:0)#, dclk/shclk, dqm(3:0), fpd(3:0), iord#, jtdo, memrd#, memwr#, mpower, pcs(4:0)#, poweron, ras#, romcs#, sa10, sdclk, sdcs(3:0)#, sysdir, sysen#, ube#, upon, vpbias/gpo63, vplcd/gpo62, we# 2. applies to the tpx(1:0) and tpy0 pins. 3. applies to the tpy1 pin. 4. applies to the following pins. fpd(9:4)/gpio(45:40), fpd(11:10)/cf1_cd(2:1)#/gpio(47:46), fpd(13:12)/cf1_ce(2:1)#/gpio(49:48), fpd14/cf1_stschg#/gpio50, fpd15/cf1_ready/gpio51, tc(1:0)#/gpio(53:52), a(22:15)/gpio(61:54) remark for details of the i/o circuits, refer to 1.4 pin i/o circuits
data sheet u16277ej1v0ds 39 pd30181a, 30181ay (2) pins of i/o circuit types b and g parameter symbol conditions min. typ. max. unit v oh2 pins of type b note 1 , i oh = ?2 ma 0.8v dd33 v output voltage, high v oh_usb pins of type g note 2 , r pd = 15 k ? 2.8 3.6 v v ol2 pins of type b note 1 , i ol = 2 ma 0.4 v output voltage, low v ol_usb pins of type g note 2 , r pu = 1.5 k ? 0.3 v v ih2 pins of type b note 1 0.75v dd33 v dd33 + 0.3 v input voltage, high v ih_usb pins of type g note 2 , single end 2.0 v v il2 pins of type b note 1 ? 0.3 0.6 v input voltage, low v il_usb pins of type g note 2 , single end 0.8 v hysteresis voltage note 3 v h pins of type b note 1 0.17v dd33 v output cross level note 4 v crs_usb pins of type g note 2 1.3 2.0 v differential input sensitivity note 4 v di_usb pins of type g note 2 0.2 v differential input common mode range note 4 v cm_usb pins of type g note 2 , v di < 200 mv 0.8 2.5 v external pull-up resistor r pu pins of type g note 2 1.425 1.575 k ? external pull-down resistor r pd pins of type g note 2 14.25 15.75 k ? external resistor for impedance adjustment note 5 r s pins of type g note 2 20.9 23.1 ? notes 1. applies to the following pins. power, rstsw#, rtcrst#, cf1_reset/dbus32, rxd0, txd0/clksel2, rxd2/irdin, txd2/irdout/mips16en, cts2#/bitclk/sclk, dtr2#/sdataout/sdo/divmode0, rts2#/sync/ws/divmode1, dcd2#/sdatain/sdi, dsr2#/sreset#, uoc, cf1_dir/kport4/gpio39, cf1_en#/kport5/gpio38, cf1_vccen#/kscan4/gpio37, cf0_cd2#/gpio36, cf0_cd1#/gpio35, cf0_iois16#/gpio34, cf_wait#/gpio33, cf0_ce2#/gpio32, cf0_ce1#/gpio31, cf0_stschg#/gpio30, cf0_ready/gpio29, cf0_reset/gpio28, cf0_dir/gpio27, cf0_en#/gpio26, cf_reg#/gpio25, cf0_vccen#/gpio24, sck/kscan11/gpio23, si/kscan10/gpio22, so/kscan9/gpio21, frm/kscan8/gpio20, rts0#/gpio19/clksel1, cts0#/gpio18, dtr0#/rts1#/gpio17/clksel0, dcd0#/gpio16, dsr0#/cts1#/gpio15, rxd1/scl1/gpio14, txd1/sda1/gpio13, scl0/kport7/gpio12, sda0/kport6/gpio11, pwm(2:0)/kscan(5:7)/gpio(10:8), kport(3:0)/gpio(7:4), kscan(3:0)/gpio(3:0) 2. applies to the uhdp, uhdn, udp, and udn pins 3. hysteresis voltage: difference between the minimum voltage at which the high level of a schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low. 4. precision tests have not been performed. only guaranteed as design characteristics. 5. the recommended value is 22 ? . remark for details of the i/o circuits, refer to 1.4 pin i/o circuits .
data sheet u16277ej1v0ds 40 pd30181a, 30181ay connection example of external resistor (a) when pulled down r s r pd uhdp, uhdn, udp, udn gndu dut (b) when pulled up r s r pu uhdp, uhdn, udp, udn vddu dut
data sheet u16277ej1v0ds 41 pd30181a, 30181ay (3) common parameter symbol conditions min. typ. max. unit fullspeed mode 350 ma fullspeed mode, program using cache operating, dma controller operating, clock supplied to pci unit 165 ma fullspeed mode, program using cache operating, dma controller operating 100 ma fullspeed mode, program not using cache operating, all peripheral bus masters stopped, all clo cks of unused units stopped 80 ma standby mode, peripheral bus master operating continuously 70 90 ma standby mode, all peripheral bus masters stopped, all clo cks of unused unit stopped 45 53 ma suspend mode 10 20 ma i dd25 note 2 hibernate mode, v dd25 = 0 v 0 0 ma 32-bit bus 45 58 ma fullspeed mode 16-bit bus 40 50 ma 32-bit bus 45 58 ma standby mode, peripheral bus master operating continuously 16-bit bus 40 50 ma standby mode, all peripheral bus masters stopped, all clo cks of unused units stopped 24ma suspend mode 2 4 ma hibernate mode, pwmu channel 0 operating 2 4 ma i dd33 note 3 hibernate mode, pwmu channel 0 stopped 25 50 a power supply current note 1 i ddad note 4 a/d, d/a converters operating 3 9 ma input leakage current note 5 i li v dd33 = 3.6 v, v i = v dd33 , 0 v 5 a output leakage current i lo v dd33 = 3.6 v, v i = v dd33 , 0 v 5 a notes 1. value when aclock = 131.1 mhz, tclock = 65.55 mhz, div2 mode. 2. i dd25 is the total current flowing to the vdd2 and vddp pins. 3. i dd33 is the total current flowing to the vdd3, vddu, vddtp, and vddo pins. 4. i ddad is the current flowing to the vddad pin when vref is supplied to the a/d and d/a converters. 5. excluding the i.c. pin. remarks 1. in suspend mode, the internal lcd controller does not operate because the memory controller (mcu) clock and lcd controller (lcu) clock are stopped. 2. each current value is the average value that flows under the specified conditions. design the power supply so that the current under the max. condition can be supplied stably (so that voltage drop or ripple do not occur in the whole system). 3. the peripheral bus master indicates the following peripheral units. lcu, dcu, iopciu, usbhu, usbfu, ac97u
data sheet u16277ej1v0ds 42 pd30181a, 30181ay data retention characteristics (t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. max. unit data retention voltage v dddr3 hibernate mode, 3.3 v power supply 2.5 3.6 v data retention high-level input voltage v ihdr hibernate mode, rtcrst# pin 0.9v dddr3 v the data retention voltage and data retention high-level input voltage are the voltages that guarantee the operation of elapsedtime counter in the rtc and the data retention of the registers (using a 3.3 v power supply) of the following peripheral units. these voltages do not apply to the data in the cpu core (using a 2.5 v power supply). pmu: pmuintreg, pmucntreg, pmuwaitreg, pmudivreg rtc: etimelreg, etimemreg, etimehreg, ecmplreg, ecmpmreg, ecmphreg giu: gpmode0, gpmode1, gpmode2, gpmode3, gpmode4, gpmode5, gpmode6, gpmode7, gpdata0, gpdata1, gpdata2, gpdata3, gpinen0, gpinen1, gpinen2, gpinen3, gpintmsk0, gpintmsk1, gpintmsk2, gpintmsk3, gpinttyp0, gpinttyp1, gpinttyp2, gpinttyp3, gpinttyp4, gpinttyp5, gpinttyp6, gpinttyp7, gpintstat0, gpintstat1, gpintstat2, gpintstat3, pinmode, sdramact, nvreg0, nvreg1, nvreg2, nvreg3 pwmu: pwm0atsreg, pwm0iatsreg, pwm0cntreg, pwm0astcreg, pwm0intreg, pwm1ctrl, pwm1buf
data sheet u16277ej1v0ds 43 pd30181a, 30181ay ac characteristics (t a = ? 40 to +85 c, v dd25 = 2.3 to 2.7 v, v dd33 = 3.0 to 3.6 v) ac test input test points (a) d(31:0), iordy, iocs16#, drq(1:0)#, tc(1:0)#/gpio(53:52), nmi#, hsync/loclk/nwireen, vsync/flm/bmode1, fpd15/cf1_ready/gpio51, fpd14/cf1_stschg#/gpio50, fpd(13:12)/cf1_ce(2:1)#/gpio(49:48), fpd(11:10)/cf1_cd(2:1)#/gpio(47:46), fpd(9:4)/gpio(45:40), clk48, jtck, jtms, jtdi/rmode#, jtrst#, bktgio#, tpx(1:0), tpy(1:0) (b) a(22:15)/gpio(61:54), power, rstsw#, rtcrst#, cf1_reset/dbus32, rxd0, txd0/clksel2, rxd2/irdin, txd2/irdout/mips16en, cts2#/bitclk/sclk, dtr2#/sdataout/sdo/divmode0, rts2#/sync/ws/divmode1, dcd2#/sdatain/sdi, dsr2#/sreset#, uoc, cf1_dir/kport4/gpio39, cf1_en#/kport5/gpio38, cf1_vccen#/kscan4/gpio37, cf0_cd(2:1)#/gpio(36:35), cf0_iois16#/gpio34, cf_wait#/gpio33, cf0_ce(2:1)#/gpio(32:31), cf0_stschg#/gpio30, cf0_ready/gpio29, cf0_reset/gpio28, cf0_dir/gpio27, cf0_en#/gpio26, cf_reg#/gpio25, cf0_vccen#/gpio24, sck/kscan11/gpio23, si/kscan10/gpio22, so/kscan9/gpio21, frm/kscan8/gpio20, rts0#/gpio19/clksel1, cts0#/gpio18, dtr0#/rts1#/gpio17/clksel0, dcd0#/gpio16, dsr0#/cts1#/gpio15, rxd1/scl1/gpio14, txd1/sda1/gpio13, scl0/kport7/gpio12, sda0/kport6/gpio11, pwm(2:0)/kscan(5:7)/gpio(10:8), kport(3:0)/gpio(7:4), kscan(3:0)/gpio(3:0) 2.0 v 0.25v dd33 2.0 v 0.25v dd33 test points v dd33 0 v input pins 0.75v dd33 0.25v dd33 0.75v dd33 0.25v dd33 test points v dd33 0 v input pins
data sheet u16277ej1v0ds 44 pd30181a, 30181ay ac test output test points load condition dut all output pins c l = 50 pf v dd33 all output pins 0 v 0.5v dd33 0.5v dd33 test points
data sheet u16277ej1v0ds 45 pd30181a, 30181ay (1) clock parameters parameter symbol conditions min. typ. max. unit clksel(2:0) = 111 note 147.4 mhz clksel(2:0) = 110 131.1 mhz clksel(2:0) = 101 118.0 mhz clksel(2:0) = 100 98.3 mhz clksel(2:0) = 011 90.7 mhz clksel(2:0) = 010 84.1 mhz clksel(2:0) = 001 78.5 mhz cpu core operating frequency f aclock clksel(2:0) = 000 73.7 mhz divmode(1:0) = 11 note 18.432 f aclock /1 65.55 mhz divmode(1:0) = 10 18.432 f aclock /2 65.55 mhz divmode(1:0) = 01 18.432 f aclock /3 65.55 mhz tclock, sdclk frequency f tclock divmode(1:0) = 00 note 18.432 f aclock /4 65.55 mhz masterout frequency f masterout f tclock /4 mhz pciclkdiv(1:0) = 00 f tclock /8 32.78 mhz pciclkdiv(1:0) = 01 f tclock /4 32.78 mhz pciclkdiv(1:0) = 10 note f tclock /2 32.78 mhz pciclock frequency t pciclock pciclkdiv(1:0) = 11 note f tclock /1 32.78 mhz lclkdiv(1:0) = 11 note f tclock /1 mhz lclkdiv(1:0) = 01 f tclock /2 mhz lclkdiv(1:0) = 10 f tclock /3 mhz lclock frequency f lclock lclkdiv(1:0) = 00 f tclock /4 mhz pclkdiv(1:0) = 00 18.432 f tclock /1 32.78 mhz pclkdiv(1:0) = 01 18.432 f tclock /2 32.78 mhz pclkdiv(1:0) = 10 18.432 f tclock /4 32.78 mhz pclock frequency f pclock pclkdiv(1:0) = 11 note 18.432 f tclock /8 32.78 mhz ecusysclkdiv(1:0) = 00 note f tclock /1 32.78 mhz ecusysclkdiv(1:0) = 01 f tclock /2 32.78 mhz ecusysclkdiv(1:0) = 10 f tclock /4 32.78 mhz ecu_sysclock frequency f ecu_sysclock ecusysclkdiv(1:0) = 11 f tclock /8 32.78 mhz note these values cannot be set in the current v r 4181a. remarks 1. the settings of the clksel(2:0) and divmode(1:0) signals are sampled when the rtcrst# signal changes to high level. 2. pciclkdiv(1:0): bits 9 and 8 of the clkdivctrl register in the ccu. set these bits before starting use of the on-chip peripheral pci unit. 3. lclkdiv(1:0): bits 5 and 4 of the exibucfg register in the exibu. set these bits before setting the timing parameters for each register of the exibu. 4. pclkdiv(1:0): bits 1 and 0 of the clkdivctrl register in the ccu. 5. ecusysclkdiv(1:0): bits 5 and 4 of the clkdivctrl register in the ccu. set these bits before starting use of the ecu.
data sheet u16277ej1v0ds 46 pd30181a, 30181ay (2) reset parameters parameter symbol conditions min. max. unit rtc reset input low-level width t wrsl applies to rtcrst# signal 600 ms rstsw reset input low-level width t wrswl applies to rstsw# signal 100 s remark if the low-level width of reset input is the min. value or lower, a reset sequence may not be started. rtcrst# (input) t wrsl rstsw# (input) t wrswl (3) initial setting parameters parameter symbol conditions min. max. unit setup time (to rtcrst# )t ss 91.6 s hold time (from rtcrst# )t sh ? 10 s t ss t sh hi-z normal operation rtcrst# (input) nwireen, bmode(1:0), dbus32, clksel(2:0), mips16en, divmode(1:0) (input) remark the circles indicate the sampling timing.
data sheet u16277ej1v0ds 47 pd30181a, 30181ay (4) sdram, syncflash interface (mcu) parameters parameter symbol conditions min. max. unit sdclk frequency f sdclk 65.55 mhz sdclk cycle t sdclk 15.26 ns sdclk high-level width t sdch 3.5 ns sdclk low-level width t sdcl 3.5 ns output delay time (from sdclk )t sddp 1.5 11.7 ns data setup time t sds 6.2 ns data hold time t sdh 2.9 ns sdclk (output) a(14:11), sa10, a(9:0) (output) d(31:0) (write) d(31:0) (read) cke(1:0), sdcs(3:0)#, dqm(3:0), ras#, cas#, we# (output) t sds t sdh hi-z hi-z t sdclk t sdcl t sdch t sddp remark the circles indicate the sampling timing.
data sheet u16277ej1v0ds 48 pd30181a, 30181ay (5) rom, flash memory, sram, isa interface (exibu) parameters parameter symbol conditions min. max. unit tclock frequency f tclock 65.55 mhz tclock cycle t tclock 15.26 ns lclock frequency f lclock 32.78 mhz lclock cycle t lclock 30.52 ns output delay time t exd 012ns data input setup time t exs 5ns data input hold time t exh 0ns data output float delay time t exz 10 ns data output setup time (from command signal ) t excl 0ns iordy input hold time t exrdyh 0ns iocs16# input hold time t excs16h 0ns drqn# input inactive setup time t drqneg 20 ns remarks 1. n = 0, 1 2. tclock is generated by dividing aclock in accordance with the setting of the divmode(1:0) signals when the rtcrst# signal changes to high level. after releasing the rtc reset, the division ratio of tclock can be changed by setting the pmudivreg register. 3. lclock is generated by dividing tclock in accordance with the setting of the lclkdiv(1:0) bits of the exibucfg register in the exibu. 4. the memrd#, memwr#, iord#, and iowr# signals are called as command signals for the external system bus interface.
data sheet u16277ej1v0ds 49 pd30181a, 30181ay (a) non-ready mode timing hi-z hi-z t exs t exh t excl conset+t exd t tclock +t exd t tclock +t exd conwid+t exd csoff +t exd busidle +t exd t exd t exd t exd t exz t exd a(24:0), ube# (output) romcs#, pcs(4:0)# (output) iord#, iowr#, memrd#, memwr# (output) sysdir (output) sysen# (output) d(31:0) (write) d(31:0) (read) note note input note output remarks 1. conset, conwid, csoff, and busidle are the timing parameters that can be changed by setting registers of the exibu. each timing parameter is defined as the number of lclock cycles. 2. the circles indicate the sampling timing.
data sheet u16277ej1v0ds 50 pd30181a, 30181ay (b) page access timing (conset = 0, csoff = 0) conwid+t exd subcwid +t exd t tclock +t exd t exd t exd a(24:0), ube# (output) romcs#, pcs(4:0)# (output) iord#, iowr#, memrd#, memwr# (output) sysdir (output) sysen# (output) d(31:0) (write) d(31:0) (read) t exh t exs t exd t exd t exz output t exd t exd t exd t exh t exs t exh t exs t exh t exs note note note note subcwid +t exd subcwid +t exd note input remarks 1. conwid and subcwid are the timing parameters that can be changed by setting registers of the exibu. each timing parameter is defined as the number of lclock cycles. 2. the circles indicate the sampling timing. 3. the broken lines indicate high impedance.
data sheet u16277ej1v0ds 51 pd30181a, 30181ay (c) ready mode timing (rdysyn = 1) hi-z hi-z t exs t exh t excl t exrdyh 2t tclock +t lclock +t exd t tclock +t exd t tclock +t exd csoff +t exd conoff +t exd rminwid +t exd conset +t exd busidle +t exd t exd t exd t exd t exz t exd a(24:0), ube# (output) romcs#, pcs(4:0)# (output) iord#, iowr#, memrd#, memwr# (output) sysdir (output) iordy (input) sysen# (output) d(31:0) (write) d(31:0) (read) note note input note output remarks 1. conset, csoff, rminwid, conoff, and busidle are the timing parameters that can be changed by setting registers of the exibu. each timing parameter is defined as the number of lclock cycles. 2. the circles indicate the sampling timing.
data sheet u16277ej1v0ds 52 pd30181a, 30181ay (d) external isa bus space access (ready mode) timing (rdysyn = 1) hi-z hi-z hi-z t exs t exh t excl t exrdyh 2t tclock +t lclock +t exd t excs16h t lclock +t exd t tclock +t exd t tclock +t exd csoff +t exd conoff +t exd conset +t exd iocs16set +t exd busidle +t exd t exd t exd t exd t exz t exd a(24:0), ube# (output) iord#, iowr#, memrd#, memwr# (output) sysdir (output) iordy (input) iocs16# (input) sysen# (output) d(15:0) (write) d(15:0) (read) note note rminwid +t exd t exd input note output remarks 1. iocs16set, conset, csoff, rminwid, conoff, and busidle are the timing parameters that can be changed by setting registers of the exibu. each timing parameter is defined as the number of lclock cycles. 2. the circles indicate the sampling timing.
data sheet u16277ej1v0ds 53 pd30181a, 30181ay (e) dma transfer timing hi-z hi-z t exs t exh t drqneg t excl t tclock +t exd t tclock +t exd csoff +t exd conwid+t exd conset+t exd busidle +t exd t exd t exd t exd t exz t exd a(24:0), ube# (output) romcs#, pcs(4:0)# (output) iord#, iowr#, memrd#, memwr# (output) sysdir (output) drqn# (input) dakn# (output) sysen# (output) d(31:0) (write) d(31:0) (read) note note input note output remarks 1. conset, conwid, csoff, and busidle are the timing parameters that can be changed by setting registers of the exibu. each timing parameter is defined as the number of lclock cycles. 2. the circles indicate the sampling timing. 3. n = 0, 1
data sheet u16277ej1v0ds 54 pd30181a, 30181ay (6) compactflash/pc card/ata (ide) interface (ecu) parameters parameter symbol conditions min. max. unit tclock frequency f tclock 65.55 mhz tclock cycle t tclock 15.26 ns lclock frequency f lclock 32.78 mhz lclock cycle t lclock 30.52 ns ecu_sysclock frequency f ecu_sysclock 32.78 mhz ecu_sysclock cycle t ecu_sysclock 30.52 ns output delay time (exibu) t exd 012ns output delay time (ecu) t ecud 0tbdns data input setup time t exs 5ns data input hold time t exh 0ns data output float delay time t exz 10 ns data output setup time (to command signal ) t excl 0ns cf_wait# input hold time t ecurdyh 0ns cf0_iois16# input hold time t ecucs16h 0ns remarks 1. tclock is generated by dividing aclock in accordance with the setting of the divmode(1:0) signals when the rtcrst# signal changes to high level. after releasing the rtc reset, the division ratio of tclock can be changed by setting the pmudivreg register. 2. lclock is generated by dividing tclock in accordance with the setting of the lclkdiv(1:0) bits of the exibucfg register in the exibu. 3. ecu_sysclock is generated by dividing tclock in accordance with the setting of the ecusysclkdiv(1:0) bits of the clkdivctrl register in the ccu. 4. memrd#, memwr#, iord#, and iowr# signals are called as command signals for the external system bus interface. (a) relationship between ecu bus cycle type and ecuwait ecuwait value (ns) bus cycle number of wait cycles min. max. 16-bit i/o cycle (ionwt = 1) 2 t ecu_sysclock 2 16-bit i/o cycle(ionwt = 0) 3 t ecu_sysclock 3 8-bit i/o cycle (wn_iows = 1) 4 t ecu_sysclock 4 8-bit i/o cycle (wn_iows = 0) 5 t ecu_sysclock 5 16-bit memory cycle (zwsen = 1 and m16w(1:0) = 0) 0 16-bit memory cycle (zwsen = 0 and m16w(1:0) = n) n + 1 t ecu_sysclock (n + 1) 8-bit memory cycle (zwsen = 1) 0 0 8-bit memory cycle (zwsen = 0) 5 t ecu_sysclock 4 remarks 1. ionwt, wn_iows, zwsen, and m16w(1:0) are bits of the register in the ecu. 2. n = 0, 1
data sheet u16277ej1v0ds 55 pd30181a, 30181ay (b) external isa bus space access (ready mode) timing (rdysyn = 1) hi-z hi-z hi-z t exs t exh t excl t ecurdyh t tclock +t lclock +t ecu_sysclock +t ecud t ecucs16h t lclock +t ecud t tclock +t exd t tclock +t ecud t tclock +t ecud t tclock +t exd csoff +t exd conoff +t exd ecuwait +t ecud conset +t exd iocs16set +t exd busidle +t exd t exd t ecud t ecud t exd t exz t exd a(24:0), ube# (output) iord#, iowr#, memrd#, memwr# (output) sysdir (output) cf0_iois16# (input) cf_wait# (input) sysen# (output) cfn_ce(2:1)#, cf_reg# (output) cfn_en# (output) cfn_dir (output) d(15:0) (write) d(15:0) (read) note note rminwid +t exd input t tclock +t ecud t tclock +t ecud t exd t exd note output remarks 1. iocs16set, conset, csoff, rminwid, conoff, and busidle are the timing parameters that can be changed by setting registers of the exibu. each timing parameter is defined as the number of lclock cycles. 2. the circles indicate the sampling timing. 3. n = 0, 1
data sheet u16277ej1v0ds 56 pd30181a, 30181ay (7) usb interface (usbhu, usbfu) parameters parameter symbol conditions min. max. unit t r_fusb fullspeed (12 mbps) mode 4 20 ns rise time note 1 t r_lusb low speed (1.5 mbps) mode 75 300 ns t f_fusb fullspeed (12 mbps) mode 4 20 ns fall time note 1 t f_lusb low speed (1.5 mbps) mode 75 300 ns t rfm_fusb fullspeed (12 mbps) mode 90 111 % vp-p output potential width notes 1 , 2 t rfm_lusb low speed (1.5 mbps) mode 80 125 % notes 1. precision tests have not been performed. only guaranteed as design characteristics. 2. indicated by the following expressions. t rfm_fusb = t r_fusb /t f_fusb t rfm_lusb = t r_lusb /t f_lusb t r_fusb t r_lusb uhdp, uhdn udp, udn (i/o) 90% 10% t f_fusb t f_lusb 90% 10%
data sheet u16277ej1v0ds 57 pd30181a, 30181ay (8) ac97 interface (ac97u) parameters parameter symbol conditions min. typ. max. unit bitclk frequency f bitclk 12.288 mhz bitclk cycle t bitclk 81.4 ns bitclk high-level width t bitclkh 36 40.7 45 ns bitclk low-level width t bitclkl 36 40.7 45 ns sync frequency f sync 48 khz sync cycle t sync 20.8 s sync high-level width t synch 1.3 s sync low-level width t syncl 19.5 s sdatain input setup time (to bitclk ) t sdats 10 ns sdatain input hold time (to bitclk ) t sdath 10 ns sdataout output delay time (to bitclk ) t sdatd 25 ns t sdats t sdatd t sync t synch t sdatd t sdath t bitclk t bitclkh bitclk (input) sdatain (input) sdataout (output) sync (output) t bitclkl t syncl
data sheet u16277ej1v0ds 58 pd30181a, 30181ay (9) i 2 s interface (i2su) parameters parameter symbol conditions min. max. unit sclk frequency f sclk 6.114 mhz sclk cycle t sclk 163 ns sclk high-/low-level width t sclkhl t sclk /2 ? 20 t sclk /2 + 20 ns sdi input setup time (to sclk )t sdis 30 ns sdi input hold time (from sclk )t sdih 30 ns sdo output delay time (from sclk )t sdod 30 ns ws delay time (from sclk )t wsd 30 ns t sdis t sdod t sdod t sdih t sclk t sclkhl t wsd sclk (i/o) ws (i/o) sdi (input) sdo (output) t sclkhl
data sheet u16277ej1v0ds 59 pd30181a, 30181ay (10) serial interface (siu) parameters parameter symbol conditions min. max. unit txd0, txd1, txd2 output pulse width t txd n ? 0.1 n + 0.1 s rxd0, rxd1, rxd2 input pulse width t rxd (9/16) n s irdout high-level output pulse width t irdout (3/16) n ? 0.1 (3/16) n + 0.1 s irdin input pulse width t irdin 1 s remark n is the data transfer cycle per bit determined by the divisor of the baud rate generator set in the siudll and siudlm registers. baud rate (bps) divisor (dlm(7:0)||dll(7:0)) n ( s) 50 23040 20000.00 75 15360 13333.33 110 10473 9090.91 134.5 8565 7434.94 150 7680 6666.67 300 3840 3333.33 600 1920 1666.67 1200 960 833.33 1800 640 555.56 2000 576 500.00 2400 480 416.67 3600 320 277.78 4800 240 208.33 7200 160 138.89 9600 120 104.17 19200 60 52.08 38400 30 26.04 57600 20 17.36 115200 10 8.68 128000 9 7.81 144000 8 6.94 192000 6 5.21 230400 5 4.34 288000 4 3.47 384000 3 2.60 576000 2 1.74 1152000 1 0.868 remark baud rate = (18.432 mhz/16)/(value set in the siudlm or siudll register)
data sheet u16277ej1v0ds 60 pd30181a, 30181ay remark n = 0 to 2 txdn (output) t txd rxdn (input) irdout (output) irdin (input) t rxd t irdout t irdin
data sheet u16277ej1v0ds 61 pd30181a, 30181ay (11) i 2 c bus interface (i2cu) parameters ( pd30181ay only) normal mode high-speed mode parameter symbol condition min. max. min. max. unit scln frequency f scl 0 100 0 400 khz start condition hold time t hd:sta 4.0 0.6 s scln low-level width t low 4.7 1.3 s scln high-level width t high 4.0 0.6 s rise time t rc 1.0 0.3 s fall time t fc 0.3 0.3 s data setup time t su:dat 0.25 0.1 s data retention time t hd:dat 00 s repeat start setup time t su:sta 4.7 0.6 s stop condition setup time t su:sto 4.0 0.6 s bus release time t buf 4.7 1.3 s t fc t hd:sta t low t high t su:dat t rc t su:sta t rc t fc sdan (i/o) scln (i/o) t hd:dat t su:sto t buf remark n = 0, 1
data sheet u16277ej1v0ds 62 pd30181a, 30181ay (12) clocked serial interface (csi) parameters parameter symbol condition min. max. unit sck frequency f sck 4.608 mhz sck cycle t sck 217 ns sck high-/low-level width t sckhl t sck /2 ? 20 t sck /2 + 20 ns si input setup time (to sck edge note )t sis 50 ns si input hold time (from sck edge note )t sih 50 ns so output delay time (from sck edge note ) t sod 50 ns note the sck edge used differs depending on the settings of the ckmd and ckpol bits of the csimode register. t sis t sod t sih t sck t sckhl sck (i/o) si (input) so (output) t sckhl remark this diagram shows the timing when using the sck rising edge (ckmd = 0 and ckpol = 0, or ckmd = 1 and ckpol = 1).
data sheet u16277ej1v0ds 63 pd30181a, 30181ay (13) lcd interface (lcu) parameters parameter symbol condition min. max. unit dclk/shclk frequency f dclk 32.775 mhz dclk/shclk cycle t dclk 30 ns dclk/shclk high-/low-level width t dclkhl t dclk /2 ? 5t dclk /2 + 5 ns output delay time (from dclk/shclk edge note ) t lcdd applies to hsync/loclk, vsync/flm, enab/m, and fpd(15: 0) signals 30 ns note the dclk/shclk edge used differs depending on the setting of the sclkpol bit of the lcdctrlreg register. t lcdd t dclk t dclkhl dclk/shclk (output) hsync/loclk, vsync/flm, enab/m, fpd(15:0) (output) t dclkhl remark this diagram shows the timing when using the dclk/shclk rising edge (sclkpol = 1).
data sheet u16277ej1v0ds 64 pd30181a, 30181ay (14) gpio interface (giu) parameters parameter symbol condition min. max. unit t gpin1 restoring from hibernate mode when level trigger is selected. 100 s gpio input level width t gpin2 interrupt input when level trigger is selected. (t tclock 4) 3 ns t gpinr gpio(61:40) pins 10 ns gpio input rise time note t gpinr2 gpio pins other than above 200 ns t gpinf gpio(61:40) pins 10 ns gpio input fall time note t gpinf2 gpio pins other than above 200 ns note precision tests have not been performed. only guaranteed as design characteristics. (a) gpio input level width remark n = 0 to 61 (b) gpio input rise/fall time remark n = 0 to 61 t gpin1, t gpin2 gpion (input) gpion (input) t gpinf , t gpinf2 t gpinr , t gpinr2
data sheet u16277ej1v0ds 65 pd30181a, 30181ay (15) nmi parameters parameter symbol condition min. max. unit nmi# input low-level width t nmi 100 s t nmi nmi# (input)
data sheet u16277ej1v0ds 66 pd30181a, 30181ay a/d converter characteristics (t a = ?40 to +85 c, v dd25 = 2.3 to 2.7 v, v dd33 = 3.0 to 3.6 v) parameter symbol condition min. typ. max. unit zero-scale error notes 1, 2 zse 4.0 lsb full-scale error notes 1, 2 rse 5.0 lsb integral linearity error notes 1, 2 inl 3.0 lsb differential linearity error notes 1, 2 dnl 3.0 lsb analog input voltage note 1 vian ? 0.3 v ddad + 0.3 v analog input equivalent resistance note 1 r ain 1.53 k ? analog input equivalent capacitance note 1 c ain 6.5 pf analog signal source allowable output impedance note 1 r exout when pin input capacitance c i = 3 pf 3.5 k ? notes 1 . applies to tpx(1:0), tpy(1:0), and ain(3:0) pins. 2. excluding quantization error. remark lsb: least significant bit v ddad : voltage supplied to vddad pin a/d converter input equivalent circuit r exout r ain ainn c i v r 4181a c ain remark n = 0 to 3
data sheet u16277ej1v0ds 67 pd30181a, 30181ay d/a converter characteristics (t a = ?40 to +85 c, v dd25 = 2.3 to 2.7 v, v dd33 = 3.0 to 3.6 v) parameter symbol condition min. typ. max. unit integral linearity error notes 1, 2 inl 3.0 lsb differential linearity error notes 1, 2 dnl 3.0 lsb string unit resistor r st 4 ? string output equivalent resistor r stout 1110 ? notes 1. applies to aout pin. 2. excluding quantization error. remark lsb: least significant bit cautions 1. the output impedance of the d/a converter is too large to latch the current from aout pin. if the load input impedance is small, insert a buffer amplifier between the load and the aout pin. make the wiring between the buffer amplifier and load as short as possible. if the wiring is long, processing is required such as enclosing the wiring in a with ground pattern. 2. the output voltage of the d/a converter changes in steps, so use the output signal from the d/a converter after passing it through a low pass filter. d/a converter output equivalent circuit r stout aout vddad series resistor string gndad v r 4181a 0 1023 1/2 r st 1/2 r st r st tap selector remark the series resistor string is connected between the reference voltage for the a/d converter (vddad) and gnd (gndad) for the a/d converter. to make the 1024 equivalent voltage steps between the two pins, this circuit consists of 1023 equivalent unit resistors (r st ) and two resistors with a resistance of half r st . the equivalent output impedance of the aout pin is the value calculated by adding r stout to the total r st value corresponding to the selected voltage step.
data sheet u16277ej1v0ds 68 pd30181a, 30181ay 3. package drawing s wb y1 s s wa s y s e x bab m ? e d zd a a2 a1 ze index mark a s b 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v item dimensions d e w a a1 a2 e 16.00 0.10 16.00 0.10 0.80 0.08 0.10 0.20 1.20 1.20 0.20 0.35 0.06 1.48 0.10 1.13 p240f1-80-ga3 0.50 +0.05 ?0.10 (unit:mm) x y y1 zd ze b 240-pin plastic fbga (16x16)
data sheet u16277ej1v0ds 69 pd30181a, 30181ay 4. recommended soldering conditions the pd30181a and 30181ay should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to our document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 4-1. soldering conditions for surface-mount type (a) pd30181af1-131-ga3: 240-pin plastic fbga (16 16) pd30181ayf1-131-ga3: 240-pin plastic fbga (16 16) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds or less (210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 20 hours) ir35-203-2 note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. (b) pd30181af1-131-ga3-a note : 240-pin plastic fbga (16 16) pd30181ayf1-131-ga3-a note : 240-pin plastic fbga (16 16) for soldering methods and conditions, contact an nec sales representative. note lead-free product
data sheet u16277ej1v0ds 70 pd30181a, 30181ay notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. reference document electrical characteristics for microcomputer (u15170j) note note this document number is that of the japanese version. the documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. eeprom, v r 4120, v r 4181a, v r series, and v r 4100 series are trademarks of nec corporation. mips is a registered trademark of mips technologies, inc. in the united states. syncflash is a trademark of micron technology, inc. bluetooth is a trademark of bluetooth sig, inc.
data sheet u16277ej1v0ds 71 pd30181a, 30181ay regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ?sucursal en espa?a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 ?succursale fran?aise ?filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 ?branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ?branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 ?united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290

exporting this product or equipment that includes this product may require a governmental license from the u.s.a. for some countries because this product utilizes technologies limited by the export control regulations of the u.s.a. m8e 00. 4 the information in this document is current as of july, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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